公开(公告)号：US11588046B2

公开(公告)日：2023-02-21

申请号：US17386729

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchul Shin ,  Boram Kim ,  Younghwan Park ,  Jongseob Kim ,  Joonyong Kim ,  Junhyuk Park ,  Jaejoon Oh ,  Minchul Yu ,  Soogine Chong ,  Sunkyu Hwang ,  Injun Hwang

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A high electron mobility transistor (HEMT) includes a channel layer, a plurality of barrier layers, and a p-type semiconductor layer. The barrier layers have an energy band gap greater than that of the channel layer. A gate electrode is arranged on the p-type semiconductor layer. A source electrode and a drain electrode are apart from the p-type semiconductor layer and the gate electrode on the barrier layers. Impurity concentrations of the barrier layers are different from each other in a drift area between the source electrode and the drain electrode.

公开(公告)号：US12288738B2

公开(公告)日：2025-04-29

申请号：US17227850

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Park ,  Jongseob Kim ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L29/20

Abstract: Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

公开(公告)号：US11888059B2

公开(公告)日：2024-01-30

申请号：US17349327

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7803 ,  H01L29/7831

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

公开(公告)号：US11069802B2

公开(公告)日：2021-07-20

申请号：US16703128

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

公开(公告)号：US12199174B2

公开(公告)日：2025-01-14

申请号：US17537989

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk Park ,  Sunkyu Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Woochul Jeon

IPC: H01L29/778 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

公开(公告)号：US11728419B2

公开(公告)日：2023-08-15

申请号：US17082478

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun Hwang ,  Jaejoon Oh ,  Soogine Chong ,  Jongseob Kim ,  Joonyong Kim ,  Junhyuk Park ,  Sunkyu Hwang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

Abstract: A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.

公开(公告)号：US11581269B2

公开(公告)日：2023-02-14

申请号：US16868745

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Park ,  Jongseob Kim ,  Joonyong Kim ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang ,  Injun Hwang

IPC: H01L23/00 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

Abstract: A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

公开(公告)号：US12278281B2

公开(公告)日：2025-04-15

申请号：US17475700

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Jaejoon Oh ,  Jongseob Kim

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47

Abstract: A high electron mobility transistor (HEMT) includes an active region, in which a channel is formed, and a field region surrounding the active region. The HEMT may include a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer. The gate may protrude from the active region to the field region on the barrier layer. The gate may include a first gate and a second gate. The first gate may be in the active region and the second gate may be in the boundary region between the active region and the field region. A work function of the second gate may be different from a work function of the first gate.

公开(公告)号：US12218206B2

公开(公告)日：2025-02-04

申请号：US17685886

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Jongseob Kim

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A method of manufacturing a power semiconductor device includes forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate hole, a source hole, and a drain hole penetrating the passivation layer in a same process step; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern may be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern may have a step difference.

公开(公告)号：US12119397B2

公开(公告)日：2024-10-15

申请号：US17465212

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Jaejoon Oh ,  Injun Hwang

IPC: H01L29/00 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66431

Abstract: A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.