Electronic circuit for configuring amplifying circuit configured to output voltage including low noise

    公开(公告)号:US11503239B2

    公开(公告)日:2022-11-15

    申请号:US16822930

    申请日:2020-03-18

    Abstract: An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.

    Image sensor
    12.
    发明授权

    公开(公告)号:US11363231B2

    公开(公告)日:2022-06-14

    申请号:US17333712

    申请日:2021-05-28

    Abstract: An image sensor includes a pixel array including a plurality of pixels connected to row lines extending in a first direction and to column lines extending in a second direction intersecting the first direction, a ramp voltage generator configured to output a ramp voltage, a plurality of comparators, each of the plurality of comparators including a first input terminal to which the ramp voltage is input, and a second input terminal connected to one of the column lines, and a replica circuit having a same structure as a structure of a portion of the comparators. Each of the comparators includes a plurality of transistors, a first auto-zero transistor connected to the first input terminal, a second auto-zero transistor connected to the second input terminal, and wirings connected to the plurality of transistors, the first auto-zero transistor, and the second auto-zero transistor.

    IMAGE SENSOR
    13.
    发明申请

    公开(公告)号:US20220078362A1

    公开(公告)日:2022-03-10

    申请号:US17459045

    申请日:2021-08-27

    Abstract: An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

    Comparison circuit including input sampling capacitor and image sensor including the same

    公开(公告)号:US10971445B2

    公开(公告)日:2021-04-06

    申请号:US16663582

    申请日:2019-10-25

    Abstract: A comparison circuit that includes an input sampling capacitor and an image sensor including the same are provided. The comparison circuit includes an amplifier configured to receive a pixel signal and a ramp signal to perform a correlated double sampling operation, a first pixel capacitor connected to the amplifier through a first floating node and configured to transmit the pixel signal, a first ramp capacitor connected to the amplifier through a second floating node and configured to transmit the ramp signal, a second pixel capacitor connected in parallel to the first pixel capacitor, and a second ramp capacitor connected in parallel to the first ramp capacitor, wherein the second pixel capacitor is formed between the first floating node and first peripheral routing lines, and the second ramp capacitor is formed between the second floating node and second peripheral routing lines.

    IMAGE SENSOR HAVING REDUCED PARASITIC CAPACITANCE

    公开(公告)号:US20210120200A1

    公开(公告)日:2021-04-22

    申请号:US16890422

    申请日:2020-06-02

    Abstract: An image sensor, including a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a sampling circuit including a plurality of comparators, each comparator of the plurality of comparators having a first input terminal connected to a column of the column lines and a second input terminal configured to receive the ramp voltage; and an analog-to-digital converter configured to convert an output of the plurality of comparators to a digital signal, wherein the plurality of comparators include a first comparator connected to a first column line, and a second comparator connected to a second column line adjacent to the first column line in the first direction, wherein each of the first comparator and the second comparator includes a first transistor and a second transistor disposed sequentially in the second direction, and wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is different from a gap between the first transistor of the second comparator and the second transistor of the second comparator.

    Image sensors including shielding structures

    公开(公告)号:US10313616B2

    公开(公告)日:2019-06-04

    申请号:US15434605

    申请日:2017-02-16

    Abstract: An image sensor includes first pixels and second pixels arranged in alternating order along a first direction, first output lines extending in a second direction that is perpendicular to the first direction and respectively connected to the first pixels, second output lines extending in the second direction and respectively connected to the second pixels, first analog circuit blocks and second analog circuit blocks arranged in alternating order along the first direction, and shielding structures disposed each between adjacent ones of the first and second analog circuit blocks. Each of the first analog circuit blocks includes a plurality of first analog circuits respectively connected to the first output lines. Each of the second analog circuit blocks includes a plurality of second analog circuits respectively connected to the second output lines.

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