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    METHOD AND APPARATUS FOR PERFORMING HANDOVER OF CARRIER AGGREGATION MOBILE STATION
    13.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING HANDOVER OF CARRIER AGGREGATION MOBILE STATION 审中-公开
    用于执行携带者聚集移动台切换的方法和装置

    公开(公告)号：US20150237541A1

    公开(公告)日：2015-08-20

    申请号：US14620374

    申请日：2015-02-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wook KIM ,  Hyo-Joon KIM ,  Joong-Keun CHO

    IPC: H04W36/00

    CPC classification number: H04W36/0055 ,  H04W24/10 ,  H04W36/0069 ,  H04W36/0083 ,  H04W36/0088 ,  H04W36/0094 ,  H04W72/0453

    Abstract: A method of a base station (BS) of a carrier aggregation (CA) is provided. The method includes determining whether a mobile station (MS) concurrently uses a first cell associated with a first carrier frequency and a second cell associated with a second carrier frequency, and controlling a handover of the MS using a measurement configuration set corresponding to a result of the determination among a plurality of measurement configuration sets that are set for each of handover related events.

    Abstract translation: 提供了载波聚合（CA）的基站（BS）的方法。 该方法包括：确定移动站（MS）是否同时使用与第一载波频率相关联的第一小区和与第二载波频率相关联的第二小区，并且使用与对应于第二载波频率的结果相对应的测量配置集来控制MS的切换 对于切换相关事件中的每一个设置的多个测量配置集合中的确定。

    CLOCK CONTROL IN SEMICONDUCTOR SYSTEM
    18.
    发明申请
    CLOCK CONTROL IN SEMICONDUCTOR SYSTEM 审中-公开

    公开(公告)号：US20200266804A1

    公开(公告)日：2020-08-20

    申请号：US16865502

    申请日：2020-05-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YONG HWAN KIM ,  Wook KIM ,  Ji Youn KIM

    IPC: H03K3/03 ,  H03K19/003 ,  H03K19/00 ,  G06F1/08 ,  H03K3/011

    Abstract: Clock generation and control in a semiconductor system having process, voltage and temperature (PVT) variation. A semiconductor device may include at least first and second ring oscillators, each disposed at locations respectively closest to first and second logic circuits of an operation circuit, and generating first and second oscillating signals. A detecting circuit is configured to perform a predetermined logic operation on the first oscillating signal and the second oscillating signal to generate a first clock signal. A calibration circuit is configured to receive the first clock signal from the detecting circuit and perform a delay control on each of the first ring oscillator and the second ring oscillator to generate a second clock signal for operating the operation circuit.

    POWER GATING CIRCUIT FOR HOLDING DATA IN LOGIC BLOCK
    20.
    发明申请
    POWER GATING CIRCUIT FOR HOLDING DATA IN LOGIC BLOCK 审中-公开

    公开(公告)号：US20190229731A1

    公开(公告)日：2019-07-25

    申请号：US16249129

    申请日：2019-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Insub SHIN ,  Wook KIM

    IPC: H03K19/00 ,  H03K3/012 ,  H03K17/30

    Abstract: A power gating circuit includes a first switch circuit, a gate circuit, and a second switch circuit. The first switch circuit is configured to disconnect a first voltage line from a second voltage line while a logic block connected to the first voltage line is in a first operation state. The gate circuit is configured to output a control signal having a first logical value if a level of a first voltage on the first voltage line is lower than a reference level while the logic block is in the first operation state. The second switch circuit configured to connect the first voltage line to the second voltage line based on the first logical value of the control signal. The reference level is based on a type of a logic gate included in the gate circuit.

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