公开(公告)号：US20240312823A1

公开(公告)日：2024-09-19

申请号：US18371774

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Seunghun Shin ,  Jihun Jung ,  Junyeong Heo

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/8258

CPC classification number: H01L21/6836 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/8258 ,  H01L2221/68336

Abstract: Provide is a method of splitting a semiconductor chip, the method including performing a back-end-of-line (BEOL) process including forming a plurality of chip areas on a semiconductor substrate, forming a splitting area, which separates the plurality of chip areas, on the semiconductor substrate, and forming a wire on a first surface of the semiconductor substrate, forming a cutout auxiliary layer in the splitting area of the first surface of the semiconductor substrate, and performing mechanical machining by bringing a mechanical machining device into contact with the cutout auxiliary layer, wherein the cutout auxiliary layer is adjacent to the plurality of chip areas.

公开(公告)号：US12094794B2

公开(公告)日：2024-09-17

申请号：US18054295

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Seunghun Shin ,  Junyeong Heo

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US12002726B2

公开(公告)日：2024-06-04

申请号：US18112715

申请日：2023-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/3157 ,  H01L21/568 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1012 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/8185

Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.

公开(公告)号：US11694963B2

公开(公告)日：2023-07-04

申请号：US17589301

申请日：2022-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jaeeun Lee ,  Junyeong Heo

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

公开(公告)号：US11610828B2

公开(公告)日：2023-03-21

申请号：US17177725

申请日：2021-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.

公开(公告)号：US11515226B2

公开(公告)日：2022-11-29

申请号：US17117588

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Seunghun Shin ,  Junyeong Heo

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US11239171B2

公开(公告)日：2022-02-01

申请号：US16922163

申请日：2020-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jaeeun Lee ,  Junyeong Heo

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/417 ,  H01L21/762 ,  H01L27/088 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

公开(公告)号：US12218096B2

公开(公告)日：2025-02-04

申请号：US17707007

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Yoonsung Kim ,  Teakhoon Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

公开(公告)号：US12165991B2

公开(公告)日：2024-12-10

申请号：US18162878

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20240213109A1

公开(公告)日：2024-06-27

申请号：US18371714

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Chungsun Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L23/3178 ,  H01L23/291 ,  H01L24/08 ,  H01L24/16 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2924/1435 ,  H10B80/00

Abstract: Provided is a semiconductor package including a first semiconductor device including a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, and a trench extending into the first interconnect structure and a portion of the first semiconductor substrate, a second semiconductor device on the first semiconductor device, and a cover insulating layer on the first semiconductor device and a side surface of the second semiconductor device, the cover insulating layer including a first portion filling the trench included in the first semiconductor device and contacting the first semiconductor substrate.