公开(公告)号：US10658463B2

公开(公告)日：2020-05-19

申请号：US15880969

申请日：2018-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongki Jung ,  Myungil Kang ,  Yoonhae Kim ,  Kwanheum Lee

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.

公开(公告)号：US10199471B2

公开(公告)日：2019-02-05

申请号：US15059519

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok Choi ,  Hwichan Jun ,  Yoonhae Kim ,  Chulsung Kim ,  Heungsik Park ,  Doo-Young Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

公开(公告)号：US10002788B2

公开(公告)日：2018-06-19

申请号：US15145924

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Jaeran Jang ,  Yoonhae Kim

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/3115 ,  H01L29/165

CPC classification number: H01L21/76825 ,  H01L21/31155 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

公开(公告)号：US20160020159A1

公开(公告)日：2016-01-21

申请号：US14725603

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ping Hsun Su ,  Yoonhae Kim ,  Hwasung Rhee

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract translation: 提供半导体器件。 第一和第二焊盘电连接到多个测试结构。 每个测试结构包括有源区，有源图案，栅电极和电极图案。 活动区域包括圆角部分。 有源图案从半导体衬底突出并沿第一方向平行延伸。 栅电极在第二方向上跨过有源图案。 一个栅电极电连接到第一焊盘。 电极图案设置在与第一焊盘电连接的栅电极的一侧。 电极图案电连接到第二垫。 电极图案穿过有源图案。 每个测试结构中的电极图案和活性图案的重叠区域与其他测试结构中的电极图案和活动图案的重叠区域不同。

公开(公告)号：US09082739B2

公开(公告)日：2015-07-14

申请号：US14261513

申请日：2014-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ping Hsun Su ,  Yoonhae Kim ,  Hwasung Rhee

IPC: H01L21/8234 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract translation: 提供半导体器件。 第一和第二焊盘电连接到多个测试结构。 每个测试结构包括有源区，有源图案，栅电极和电极图案。 活动区域包括圆角部分。 有源图案从半导体衬底突出并沿第一方向平行延伸。 栅电极在第二方向上跨过有源图案。 一个栅电极电连接到第一焊盘。 电极图案设置在与第一焊盘电连接的栅电极的一侧。 电极图案电连接到第二垫。 电极图案穿过有源图案。 每个测试结构中的电极图案和活性图案的重叠区域与其他测试结构中的电极图案和活动图案的重叠区域不同。

公开(公告)号：US20140191312A1

公开(公告)日：2014-07-10

申请号：US14140616

申请日：2013-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhae Kim ,  Hong Seong Kang ,  Junjie Xiong ,  Yoonseok Lee ,  Youshin Choi

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract translation: 半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区， 器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触 层和蚀刻停止层。 第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。