公开(公告)号：US20240120319A1

公开(公告)日：2024-04-11

申请号：US18376028

申请日：2023-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Taeyoung LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147

Abstract: A semiconductor package includes a first semiconductor structure including a first semiconductor layer having a first active surface and a first circuit device thereon and a first inactive surface and first bonding layer; a second semiconductor structure on the first semiconductor structure and including a second semiconductor layer having a second active surface and second circuit device thereon and a second inactive surface, a second frontside bonding layer, and a second backside bonding layer on the second inactive surface; and a third semiconductor structure on the second semiconductor structure and including a third semiconductor layer having a third active surface including a third circuit device thereon and a third inactive surface, and a third bonding layer, wherein the first bonding layer is bonded to the second frontside bonding layer, and the third bonding layer is bonded to the second backside bonding layer.

公开(公告)号：US20240079340A1

公开(公告)日：2024-03-07

申请号：US18459520

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Inhyo HWANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/30505 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/33051 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/065 ,  H01L2924/1436 ,  H01L2924/2064 ,  H01L2924/2065

Abstract: A semiconductor package includes: a base substrate; an interposer disposed on the base substrate, wherein the interposer includes a plurality of recesses in a bottom surface thereof; a semiconductor chip disposed on the interposer; a plurality of interposer connection terminals between the interposer and the base substrate, wherein the plurality of interposer connection terminals electrically connect the interposer to the base substrate; and a first underfill layer disposed between the interposer and the base substrate, wherein the first underfill layer at least partially surrounds the plurality of interposer connection terminals, wherein the first underfill layer at least partially surrounds a side surface of each of the plurality of recesses and has a slope declining from the bottom surface of the interposer to a top surface of the base substrate.

公开(公告)号：US20230154819A1

公开(公告)日：2023-05-18

申请号：US18154919

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM ,  Myungkee Chung ,  Aenee Jang

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L25/0652 ,  H01L23/3128

Abstract: A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

公开(公告)号：US20220189907A1

公开(公告)日：2022-06-16

申请号：US17367995

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohyun NAM ,  Younglyong KIM

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.