公开(公告)号：US11164805B2

公开(公告)日：2021-11-02

申请号：US16814455

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim ,  Taewon Yoo

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US12237290B2

公开(公告)日：2025-02-25

申请号：US16912819

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Younglyong Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.

公开(公告)号：US12166013B2

公开(公告)日：2024-12-10

申请号：US17578621

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Younglyong Kim ,  Myungkee Chung

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

公开(公告)号：US20240030187A1

公开(公告)日：2024-01-25

申请号：US18353167

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Younglyong Kim

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L2225/06541 ,  H01L2224/05078 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/08148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/0903 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2224/03614 ,  H01L2224/03845

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads on the first substrate, and a plurality of through-electrodes extending through the first substrate and connected to the plurality of first pads, and a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second substrate, and a plurality of second pads below the second substrate and in contact with the plurality of first pads. The plurality of first pads includes a first group of first pads each including a first base layer including a first recess, and a first conductive pattern layer and a first insulating pattern layer alternately disposed in the first recess, and a second group of first pads each including a second base layer including a second recess, and a second conductive pattern layer disposed in the second recess.

公开(公告)号：US11817443B2

公开(公告)日：2023-11-14

申请号：US17541869

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/14

Abstract: Disclosed is a semiconductor package including a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip, a dummy chip on the first semiconductor chip, and a dielectric layer between the first semiconductor chip and the dummy chip. A top surface of the first semiconductor chip may be lower than a top surface of the second semiconductor chip. The dielectric layer may include an inorganic dielectric material.

公开(公告)号：US11676875B2

公开(公告)日：2023-06-13

申请号：US17488662

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim ,  Taewon Yoo

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/29 ,  H01L23/3114 ,  H01L24/13

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US20220093582A1

公开(公告)日：2022-03-24

申请号：US17541869

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538

Abstract: Disclosed is a semiconductor package including a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip, a dummy chip on the first semiconductor chip, and a dielectric layer between the first semiconductor chip and the dummy chip. A top surface of the first semiconductor chip may be lower than a top surface of the second semiconductor chip. The dielectric layer may include an inorganic dielectric material.

公开(公告)号：US20210111140A1

公开(公告)日：2021-04-15

申请号：US16912819

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Younglyong Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.