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    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210135001A1

    公开(公告)日：2021-05-06

    申请号：US17140786

    申请日：2021-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong II BAE

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

    Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200303538A1

    公开(公告)日：2020-09-24

    申请号：US16894270

    申请日：2020-06-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong Il BAE

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

    Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

    SEMICONDUCTOR DEVICES
    14.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250107159A1

    公开(公告)日：2025-03-27

    申请号：US18977287

    申请日：2024-12-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Soojin JEONG ,  Myunggil KANG ,  Junggil YANG ,  Junbeom PARK

    IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE
    15.
    发明公开
    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230335552A1

    公开(公告)日：2023-10-19

    申请号：US18212304

    申请日：2023-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggil YANG ,  Minju KIM ,  Donghyi KOH

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851

    Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

    INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING THE SAME
    17.
    发明公开
    INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230163214A1

    公开(公告)日：2023-05-25

    申请号：US18093877

    申请日：2023-01-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungmin SONG ,  Bongseok SUH ,  Junggil YANG ,  Soojin JEONG

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

    CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/42392

    Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

    INTEGRATED CIRCUIT DEVICE
    18.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20220173097A1

    公开(公告)日：2022-06-02

    申请号：US17372896

    申请日：2021-07-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggil YANG ,  Minju KIM ,  Donghyi KOH

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

    Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

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