公开(公告)号：US07091630B2

公开(公告)日：2006-08-15

申请号：US10294581

申请日：2002-11-15

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H02J3/00 ,  H02J1/04

CPC分类号： H02M1/12 ,  Y10T307/422 ,  Y10T307/43

摘要： A device for inhibiting power supply voltage fluctuation that is caused by fluctuation of a load current generated by a load circuit. The device includes a current consumption circuit, a data generation circuit, and a D/A converter. The current consumption circuit is connected to a power supply and the load circuit to generate a consumption current that flows parallel to the load current of the load circuit. The data generation circuit controls the consumption current of the current consumption circuit in order to inhibit fluctuation of an output current of the power supply, which is the sum of the load current and the consumption current, when the load current rises and when the consumption current falls. The D/A converter converts the digital signal to an analog signal and provides the analog signal to the current consumption circuit.

公开(公告)号：US20060139131A1

公开(公告)日：2006-06-29

申请号：US11136556

申请日：2005-05-25

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H01P1/00

CPC分类号： H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H01L2924/00

摘要： An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS1 is formed in the upper wiring layer of the semiconductor device 1. The stub length L1 is set to a length of ¼ of the wavelength of the known frequency containing peak components of noises. The noise receiving part AT1 is disposed adjacent to the open stub OS1. The open stub OS1 is connected to the power source wiring 4 by an interlayer wiring 6. The noise receiving part AT1 is biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuit 11 and propagate (the arrow Y1 of FIG. 2) in the power source wiring 4 are reflected (arrow Y2 of FIG. 2) by the open stub OS1 so as to return to the PLL circuit 11, and do not reach the filter circuit 12.

摘要翻译： 本发明的目的是提供一种用于半导体器件的半导体器件和调整方法，其中可以减少作为无线电波辐射的电源噪声和噪声，并且可以切割半导体器件内部的电源噪声。 开放短截线OS1形成在半导体器件1的上部布线层中。 短截线长度L 1被设定为包含噪声的峰值成分的已知频率的波长的1/4的长度。 噪声接收部分AT 1设置成与开放存根OS1相邻。 开路短路OS1通过层间配线6与电源配线4连接。 噪声接收部分AT 1被偏压到接地电位。 由PLL电路11产生并传播（图2中的箭头Y 1）的基本波分量和奇数谐波在电源布线4中被反射（图2中的箭头Y 2）（图2中的箭头Y 2） 打开存根OS1，以返回到PLL电路11，并且不到达滤波电路12。

公开(公告)号：US06975522B2

公开(公告)日：2005-12-13

申请号：US10648440

申请日：2003-08-27

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： G05F1/40 ,  G06F1/04 ,  H02H7/10 ,  H03K5/14 ,  H03K5/15

CPC分类号： G06F1/04

摘要： A power fluctuation inhibiting device for effectively inhibiting fluctuation of power supply voltage that is supplied to internal circuits. The inhibiting device includes a power fluctuation measuring circuit for measuring peaks in the fluctuation of the power supply voltage produced when the internal circuits are operated. A clock signal control circuit adjusts phases of clock signals provided to respective ones of the internal circuits in accordance to the peak measuring result to substantially offset the fluctuation peaks produced when the internal circuits are operated.

摘要翻译： 一种功率波动抑制装置，用于有效地抑制供给内部电路的电源电压的波动。 抑制装置包括功率波动测量电路，用于测量内部电路工作时产生的电源电压的波动的峰值。 时钟信号控制电路根据峰值测量结果调整提供给各个内部电路的时钟信号的相位，以便基本上抵消在内部电路工作时产生的波动峰值。

公开(公告)号：US06667640B2

公开(公告)日：2003-12-23

申请号：US10106257

申请日：2002-03-27

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/04

摘要： A PLL circuit having a wide oscillation frequency range for reducing a jitter. The PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal. An oscillator generates an oscillation frequency signal having an oscillation frequency according to a control signal having a current corresponding to the phase difference signal. A detection circuit generates a detection signal by detecting the current of the control signal. A signal generation circuit generates a signal for changing the oscillation frequency of the oscillator such that the current of the control signal is within a predetermined range in accordance with the detection signal.

摘要翻译： 具有用于减少抖动的宽振荡频率范围的PLL电路。 PLL电路包括相位比较器，用于通过比较参考信号的相位与比较信号的相位来产生相位差信号。 振荡器根据具有对应于相位差信号的电流的控制信号产生具有振荡频率的振荡频率信号。 检测电路通过检测控制信号的电流来产生检测信号。 信号发生电路根据检测信号产生用于改变振荡器的振荡频率的信号，使得控制信号的电流在预定范围内。

公开(公告)号：US06538834B2

公开(公告)日：2003-03-25

申请号：US10187944

申请日：2002-07-03

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： G11B509

CPC分类号： G11B20/10009 ,  H03M1/185

摘要： A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

公开(公告)号：US20100277213A1

公开(公告)日：2010-11-04

申请号：US12837935

申请日：2010-07-16

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03L7/06 ,  H03H11/26

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805

摘要： Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.

摘要翻译： 这里公开了一种可变延迟电路，包括延迟输入信号的第一延迟部分; 输出部分 以及耦合在第一延迟部分和输出部分之间的可变阻抗部分。

公开(公告)号：US07786784B2

公开(公告)日：2010-08-31

申请号：US12042776

申请日：2008-03-05

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03H11/26

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805

摘要： Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.

摘要翻译： 这里公开了一种可变延迟电路，包括延迟输入信号的第一延迟部分; 输出部分 以及耦合在第一延迟部分和输出部分之间的可变阻抗部分。

公开(公告)号：US07619490B2

公开(公告)日：2009-11-17

申请号：US12163193

申请日：2008-06-27

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03H7/38

CPC分类号： H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H01L2924/00

摘要： An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS1 is formed in the upper wiring layer of the semiconductor device 1. The stub length L1 is set to a length of ¼ of the wavelength of the known frequency containing peak components of noises. The noise receiving part AT1 is disposed adjacent to the open stub OS1. The open stub OS1 is connected to the power source wiring 4 by an interlayer wiring 6. The noise receiving part AT1 is biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuit 11 and propagate (the arrow Y1 of FIG. 2) in the power source wiring 4 are reflected (arrow Y2 of FIG. 2) by the open stub OS1 so as to return to the PLL circuit 11, and do not reach the filter circuit 12.

摘要翻译： 本发明的目的是提供一种用于半导体器件的半导体器件和调整方法，其中可以减少作为无线电波辐射的电源噪声和噪声，并且可以切割半导体器件内部的电源噪声。 开放短截线OS1形成在半导体器件1的上部布线层中。短截线长度L1被设定为包含噪声的峰值成分的已知频率的波长的1/4。 噪声接收部分AT1设置成与开放存根OS1相邻。 开路短路OS1通过层间配线6与电源配线4连接。噪声接收部分AT1被偏置为接地电位。 从PLL电路11产生并传播（图2的箭头Y1）的基本波分量和奇数谐波在电源布线4中被反射（图2的箭头Y2） 存根OS1，以返回到PLL电路11，并且不到达滤波电路12。

公开(公告)号：US20090243627A1

公开(公告)日：2009-10-01

申请号：US12410157

申请日：2009-03-24

申请人： Kazufumi KOMURA ,  Katsumi Furukawa ,  Keiichi Fujimura ,  Takayoshi Nakamura ,  Tohru Yasuda ,  Hirohisa Nishiyama ,  Nobuyoshi Nakaya ,  Kanta Yamamoto ,  Shigetaka Asano

发明人： Kazufumi KOMURA ,  Katsumi Furukawa ,  Keiichi Fujimura ,  Takayoshi Nakamura ,  Tohru Yasuda ,  Hirohisa Nishiyama ,  Nobuyoshi Nakaya ,  Kanta Yamamoto ,  Shigetaka Asano

IPC分类号： G01R31/02

CPC分类号： G01R31/318555 ,  G01R31/318533 ,  G01R31/318552

摘要： A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

摘要翻译： 一种半导体器件包括：监测器，包括耦合在第一电源线和第二电源线之间的第一元件和用于增加第一元件与第一电源线或第二电源线之间的负载值的负载;以及 确定单元，其基于所述监视器的输出来确定所述第一元素的操作状态。

公开(公告)号：US20080036515A1

公开(公告)日：2008-02-14

申请号：US11882788

申请日：2007-08-06

申请人： Shigetaka Asano

发明人： Shigetaka Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0891

摘要： A delay adjusting circuit including a delay part in which delay elements of n+1 (n≧2) stages are connected to each other in series, a first phase comparator for detecting whether a first edge that is a transition edge of a signal of an n−1-th stage of the delay part from a first logic level to a second logic level advances from a first reference signal edge that is a transition edge of a first reference signal from the first logic level to the second logic level, a second phase comparator for detecting whether a second edge that is a transition edge of a signal of an n+1-th stage of the delay part from the first logic level to the second logic level delays from the first reference signal edge, and a delay element adjusting part that corrects a second reference signal so that the first edge advances from the first reference signal edge in the first phase comparator and the second edge delays from the first reference signal edge in the second phase comparator, and that outputs a reference bias signal for adjusting delay times of the delay elements of the delay part.

摘要翻译： 一种延迟调整电路，包括延迟部分，其中n + 1（n> = 2）级的延迟元件彼此串联连接;第一相位比较器，用于检测作为信号的过渡沿的第一边缘 从第一逻辑电平到第二逻辑电平的延迟部分的第n-1级从作为第一参考信号从第一逻辑电平到第二逻辑电平的过渡沿的第一参考信号边沿前进， 第二相位比较器，用于检测作为延迟部分的第n + 1级的信号从第一逻辑电平到第二逻辑电平的信号的转移边缘的第二边沿是否延迟第一参考信号沿;以及延迟 元件调整部分，其校正第二参考信号，使得第一边缘从第一相位比较器中的第一参考信号边缘前进，并且第二边沿从第二相位比较器中的第一参考信号边沿延迟，并且输出参考 ce偏置信号，用于调整延迟部分的延迟元件的延迟时间。