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公开(公告)号：US06873193B2
公开(公告)日：2005-03-29
申请号：US10717640
申请日：2003-11-21
IPC分类号： G01R19/165 , H03K5/08 , H03K5/153 , H03L7/00
CPC分类号： H03K17/22 , G01R19/16538 , H03K5/08 , H03K5/153
摘要： A two-level supply voltage detection circuit includes two power supply detection circuits. One of the power supply detection circuits is provided on the high potential side, and the other is provided on the lower potential side. Each power supply detection circuit outputs a detection signal which is active when the supply voltage is equal to or higher than a reference value. The two-level supply voltage detection circuit outputs an OR logic value of the detection outputs of the power supply detection circuits. Furthermore, the power supply detection circuit on the low voltage side includes a detection operation control circuit. Only when a detection signal output from the power supply detection circuit on the high voltage side is active, the detection operation control circuit turns off the power supply detection circuit on the low voltage side in response to the active detection signal.
摘要翻译： 两级电源电压检测电路包括两个电源检测电路。 电源检测电路中的一个设置在高电位侧，另一个设置在低电位侧。 每个电源检测电路输出当电源电压等于或高于参考值时有效的检测信号。 两级电源电压检测电路输出电源检测电路的检测输出的OR逻辑值。 此外，低电压侧的电源检测电路包括检测动作控制电路。 只有当从高电压侧的电源检测电路输出的检测信号有效时，检测动作控制电路就响应于主动检测信号而使低电压侧的电源检测电路断开。
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公开(公告)号：US06646342B2
公开(公告)日：2003-11-11
申请号：US10097140
申请日：2002-03-14
IPC分类号： H01L2334
CPC分类号： H01L23/50 , H01L23/5382 , H01L23/5383 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.
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公开(公告)号：US06462427B2
公开(公告)日：2002-10-08
申请号：US10024721
申请日：2001-12-21
IPC分类号： H01L2940
CPC分类号： H01L25/0652 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/19105 , H01L2924/3011 , H01L2224/05624 , H01L2924/00014
摘要： Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.
摘要翻译： 每个裸芯片IP包括具有相同尺寸和形状的相同材料的焊盘电极，并且在其几乎整个表面上以相同的间距排列成阵列。 硅布线基板包括以与裸芯片IP的焊盘电极之间相同的间距排列成几乎整个表面的阵列电极。 裸芯片IP安装在硅布线基板上，从而形成多芯片模块。
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14.发明授权Power circuit including inrush current limiter, and integrated circuit including the power circuit 有权包括浪涌电流限制器的电源电路和包括电源电路的集成电路
公开(公告)号：US6150800A
公开(公告)日：2000-11-21
申请号：US395971
申请日：1999-09-15
申请人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
发明人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
CPC分类号： G05F1/573 , G05F1/575 , Y10S323/908
摘要： A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.
摘要翻译： 描述了一种电源电路，其包括用于在电源电路的初始操作期间防止产生浪涌电流的装置，而不增加电源电路的尺寸。 电源电路包括用于从电源向输出端子提供电流的输出晶体管，以及差分放大器，用于根据预设的方式控制由输出晶体管提供的电流，以调节输出端子处的电压 参考电压。 在差分放大器的输出级的电流路径上提供限制晶体管作为源极跟随器。 使用限制晶体管的源极电位来控制输出晶体管的栅极电位。 在电源电路开始工作之前，操作控制器对电容器充电以控制限流晶体管的栅极电位，使得在电源电路的初始操作期间，通过使用电流源来放电电容器。 因此，在电源电路的初始动作期间，限制晶体管的栅极电位逐渐降低，同时输出晶体管的栅极 - 源极电压逐渐增大。 结果，可以抑制浪涌电流的产生。
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15.发明授权公开(公告)号：US07808307B2
公开(公告)日：2010-10-05
申请号：US12093393
申请日：2007-09-04
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译： 电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。 同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。 从电流镜电路10输出的两个电流分别分配给两个。 在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。 因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。 这轻而易举地减少了四分之一的必要阻力。
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公开(公告)号：US07498865B2
公开(公告)日：2009-03-03
申请号：US10511165
申请日：2004-02-19
IPC分类号： H03K3/01
CPC分类号： G05F1/565 , H03K19/00384
摘要： In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.
摘要翻译： 在本发明的半导体集成电路中，主电路2包括源极和基板彼此分离的MOS晶体管。 基板电位控制电路1控制主电路2的MOS晶体管的基板电位，使得主电路2的MOS晶体管的实际饱和电流值等于工作电源电压下的目标饱和电流值Ids Vdd。因此，即使半导体集成电路的工作电源电压降低，也可以抑制操作速度的变化。
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公开(公告)号：US06686782B2
公开(公告)日：2004-02-03
申请号：US10053552
申请日：2002-01-24
IPC分类号： H03K1722
CPC分类号： G01R19/16538 , H03K17/223
摘要： A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground. Until the output voltage from the comparison circuit is higher than the threshold voltage of the PMOS transistor, the PMOS transistor remains OFF, thereby canceling the input of the output voltage signal from the voltage division circuit to the comparison circuit. Thus, without using external components, the signal is prevented from being erroneously output due to the output voltage from the voltage division circuit rising over, without crossing, the reference voltage from the reference voltage circuit during a sharp rise of the power supply voltage.
摘要翻译： 电源电压检测电路包括用于线性分割电源电压的分压电路，用于提供参考电压的参考电压电路和用于比较来自分压电路的输出电压和参考电压的参考电压的比较电路 电压电路。 电源电压检测电路在检测到电源电压等于或高于参考电压时输出信号。 在分压电路和比较电路之间设置PMOS晶体管。 PMOS晶体管包括连接到分压电路的输出端的源极端子，连接到比较电路的输入端子的漏极端子和连接到地的栅极端子。 在比较电路的输出电压高于PMOS晶体管的阈值电压之前，PMOS晶体管保持截止状态，从而消除从分压电路到比较电路的输出电压信号的输入。 因此，在不使用外部部件的情况下，由于来自分压电路的输出电压在电源电压的急剧上升期间不与基准电压电路交叉而不会交叉，所以不会错误地输出信号。
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18.发明授权Power source system for reducing power consumption in an intermittent mode of operation 失效电源系统，用于在间歇运行模式下降低功耗公开(公告)号：US06531856B2
公开(公告)日：2003-03-11
申请号：US09920670
申请日：2001-08-03
IPC分类号： G05F140
摘要： During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.
摘要翻译： 在间歇操作模式期间，开关通常被打开，并且具有大电容的电容器与电路隔离。 在这种情况下，电源电压被间歇地供给到被驱动装置。 由于在间歇操作模式期间电容器的充电/放电电流被限制为具有小电容的电容器的充电/放电电流，所以可以降低功耗。 此外，由于在从电源电压转换电路到被驱动装置的电流路径中不存在开关，因此从电源电压转换电路向被驱动装置提供的电压不会由于开关而下降。 另一方面，在向被驱动装置连续提供电源电压的连续运转模式中，开关常闭，电容器电容器与电源系统连接。 然后降低供电电源中的噪声电平。
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公开(公告)号：US06490715B1
公开(公告)日：2002-12-03
申请号：US09550352
申请日：2000-04-14
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.
摘要翻译： 单元库数据库包括作为形成逻辑装置的基本电路的标准单元的功能信息，标准单元中的每一个包括作为逻辑端的电源端子中的至少一个，包含逻辑信息或延迟信息的标准单元的功能信息 所述电源端子相对于输出端子，或作为形成逻辑装置的功能电路的宏电池的功能信息，所述宏电池单元包括作为逻辑端子的电源端子中的至少一个，所述宏单元的功能信息包含 所述电源端子相对于输出端子的逻辑信息或延迟信息。 设计辅助系统使用单元库数据库执行逻辑仿真等。
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公开(公告)号：US08077161B2
公开(公告)日：2011-12-13
申请号：US12292131
申请日：2008-11-12
申请人： Masayoshi Kinoshita , Takeshi Sato
发明人： Masayoshi Kinoshita , Takeshi Sato
IPC分类号： G06F3/041
CPC分类号： G06F3/044
摘要： The screen-input image display device has a touch panel for outputting touched locations of a finger or the like in contact with a display panel screen; and a sensing circuit for sensing coordinates of the touched locations based on the output of the touch panel. The touch panel has a transparent conductor film which is single layer on a transparent substrate, the transparent conductor film being patterned into numerous electrode pads arranged in rows and columns of a two-dimensional matrix, and surface areas of the electrode pads vary depending on the location of the touch areas. Coordinates of the touch locations are sensed based on the proportion of charge signals of the touch locations due to differences in surface areas of the electrode pads.
摘要翻译： 屏幕输入图像显示装置具有用于输出与显示面板屏幕接触的手指等的触摸位置的触摸面板; 以及感测电路，用于基于触摸面板的输出来感测触摸位置的坐标。 触摸面板具有在透明基板上为单层的透明导体膜，透明导体膜被图案化为布置成二维矩阵的行和列的多个电极焊盘，并且电极焊盘的表面区域根据 触摸区域的位置。 触摸位置的坐标是由于由于电极焊盘的表面积的差异而导致的触摸位置的充电信号的比例而被感测的。
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