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    Screen-input image display device
    1.
    发明授权
    Screen-input image display device 有权
    屏幕输入图像显示设备

    公开(公告)号：US08077161B2

    公开(公告)日：2011-12-13

    申请号：US12292131

    申请日：2008-11-12

    申请人： Masayoshi Kinoshita ,  Takeshi Sato

    发明人： Masayoshi Kinoshita ,  Takeshi Sato

    IPC分类号： G06F3/041

    CPC分类号： G06F3/044

    摘要： The screen-input image display device has a touch panel for outputting touched locations of a finger or the like in contact with a display panel screen; and a sensing circuit for sensing coordinates of the touched locations based on the output of the touch panel. The touch panel has a transparent conductor film which is single layer on a transparent substrate, the transparent conductor film being patterned into numerous electrode pads arranged in rows and columns of a two-dimensional matrix, and surface areas of the electrode pads vary depending on the location of the touch areas. Coordinates of the touch locations are sensed based on the proportion of charge signals of the touch locations due to differences in surface areas of the electrode pads.

    摘要翻译： 屏幕输入图像显示装置具有用于输出与显示面板屏幕接触的手指等的触摸位置的触摸面板; 以及感测电路，用于基于触摸面板的输出来感测触摸位置的坐标。 触摸面板具有在透明基板上为单层的透明导体膜，透明导体膜被图案化为布置成二维矩阵的行和列的多个电极焊盘，并且电极焊盘的表面区域根据 触摸区域的位置。 触摸位置的坐标是由于由于电极焊盘的表面积的差异而导致的触摸位置的充电信号的比例而被感测的。

    Screen-input image display device
    2.
    发明申请
    Screen-input image display device 有权
    屏幕输入图像显示设备

    公开(公告)号：US20090128518A1

    公开(公告)日：2009-05-21

    申请号：US12292131

    申请日：2008-11-12

    申请人： Masayoshi Kinoshita ,  Takeshi Sato

    发明人： Masayoshi Kinoshita ,  Takeshi Sato

    IPC分类号： G06F3/045

    CPC分类号： G06F3/044

    摘要： The screen-input image display device has a touch panel for outputting touched locations of a finger or the like in contact with a display panel screen; and a sensing circuit for sensing coordinates of the touched locations based on the output of the touch panel. The touch panel has a transparent conductor film which is single layer on a transparent substrate, the transparent conductor film being patterned into numerous electrode pads arranged in rows and columns of a two-dimensional matrix, and surface areas of the electrode pads vary depending on the location of the touch areas. Coordinates of the touch locations are sensed based on the proportion of charge signals of the touch locations due to differences in surface areas of the electrode pads.

    摘要翻译： 屏幕输入图像显示装置具有用于输出与显示面板屏幕接触的手指等的触摸位置的触摸面板; 以及感测电路，用于基于触摸面板的输出来感测触摸位置的坐标。 触摸面板具有在透明基板上为单层的透明导体膜，透明导体膜被图案化为布置成二维矩阵的行和列的多个电极焊盘，并且电极焊盘的表面区域根据 触摸区域的位置。 触摸位置的坐标是由于由于电极焊盘的表面积的差异而导致的触摸位置的充电信号的比例而被感测的。

    SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS WHICH IS CAPABLE OF CONTROLLING A SUBSTRATE VOLTAGE UNDER THE LOW SOURCE VOLTAGE DRIVING OF A MINIATURIZED MOSFET
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS WHICH IS CAPABLE OF CONTROLLING A SUBSTRATE VOLTAGE UNDER THE LOW SOURCE VOLTAGE DRIVING OF A MINIATURIZED MOSFET 有权
    半导体集成电路设备，可以控制微型MOSFET的低电源电压驱动下的基极电压

    公开(公告)号：US20100117717A1

    公开(公告)日：2010-05-13

    申请号：US12686283

    申请日：2010-01-12

    申请人： Masaya Sumita ,  Shirou Sakiyama ,  Masayoshi Kinoshita

    发明人： Masaya Sumita ,  Shirou Sakiyama ,  Masayoshi Kinoshita

    IPC分类号： H03K3/01

    CPC分类号： H03K3/011 ,  G05F3/205 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

    摘要： Provided is a semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation thereof. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current. The monitor unit includes a constant current source and a monitoring MOSFET formed on the same substrate as the plurality of MOSFETs, the substrate voltage regulating unit includes a comparison unit for comparing the source potential of the monitoring MOSFET with a predetermined reference potential with the drain terminal of the monitoring MOSFET and the drain terminals of the plurality of MOSFETs connected to ground, and the substrate voltage regulating unit feeds back the output voltage output based on the comparison result by the comparison unit to the substrate voltage of the monitoring MOSFET.

    摘要翻译： 提供一种半导体集成电路装置，其能够控制MOSFET的衬底电压，使得亚阈值区域或饱和区域中的任意栅极电压值的漏极电流将不受温度依赖性和工艺变化依赖性的影响，从而提高稳定性 操作。 半导体集成电路装置包括：在半导体基板上具有多个MOSFET的集成电路主体; 监视器单元，用于监视所述多个MOSFET的至少一个漏极电流; 以及用于控制半导体衬底的衬底电压以保持漏极电流恒定的衬底电压调节单元。 监视器单元包括形成在与多个MOSFET相同的衬底上的恒流源和监视MOSFET，衬底电压调节单元包括比较单元，用于将监视MOSFET的源极电位与预定参考电位进行比较，漏极端子 的监视MOSFET和连接到地的多个MOSFET的漏极端子，并且基板电压调节单元基于比较单元的比较结果将监视MOSFET的衬底电压的输出电压输出反馈。

    Semiconductor integrated circuit apparatus which is capable of controlling a substrate voltage under low source voltage driving a miniaturized MOSFET
    4.
    发明授权
    Semiconductor integrated circuit apparatus which is capable of controlling a substrate voltage under low source voltage driving a miniaturized MOSFET 有权
    半导体集成电路装置，其能够在低源电压下控制基板电压，驱动小型化的MOSFET

    公开(公告)号：US07675348B2

    公开(公告)日：2010-03-09

    申请号：US11987709

    申请日：2007-12-04

    申请人： Masaya Sumita ,  Shirou Sakiyama ,  Masayoshi Kinoshita

    发明人： Masaya Sumita ,  Shirou Sakiyama ,  Masayoshi Kinoshita

    IPC分类号： H03K3/01

    CPC分类号： H03K3/011 ,  G05F3/205 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

    摘要： Provided is a semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation thereof. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current. The monitor unit includes a constant current source and a monitoring MOSFET formed on the same substrate as the plurality of MOSFETs, the substrate voltage regulating unit includes a comparison unit for comparing the source potential of the monitoring MOSFET with a predetermined reference potential with the drain terminal of the monitoring MOSFET and the drain terminals of the plurality of MOSFETs connected to ground, and the substrate voltage regulating unit feeds back the output voltage output based on the comparison result by the comparison unit to the substrate voltage of the monitoring MOSFET.

    摘要翻译： 提供一种半导体集成电路装置，其能够控制MOSFET的衬底电压，使得亚阈值区域或饱和区域中的任意栅极电压值的漏极电流将不受温度依赖性和工艺变化依赖性的影响，从而提高稳定性 操作。 半导体集成电路装置包括：在半导体基板上具有多个MOSFET的集成电路主体; 监视器单元，用于监视所述多个MOSFET的至少一个漏极电流; 以及用于控制半导体衬底的衬底电压以保持漏极电流恒定的衬底电压调节单元。 监视器单元包括形成在与多个MOSFET相同的衬底上的恒流源和监视MOSFET，衬底电压调节单元包括比较单元，用于将监视MOSFET的源极电位与预定参考电位进行比较，漏极端子 的监视MOSFET和连接到地的多个MOSFET的漏极端子，并且基板电压调节单元基于比较单元的比较结果将监视MOSFET的衬底电压的输出电压输出反馈。

    Semiconductor integrated circuit apparatus
    6.
    发明申请
    Semiconductor integrated circuit apparatus 有权

    公开(公告)号：US20070024345A1

    公开(公告)日：2007-02-01

    申请号：US11540757

    申请日：2006-10-02

    申请人： Masaya Sumita ,  Shirou Sakiyama ,  Masayoshi Kinoshita

    发明人： Masaya Sumita ,  Shirou Sakiyama ,  Masayoshi Kinoshita

    IPC分类号： H03K3/01

    CPC分类号： H03K3/011 ,  G05F3/205 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

    摘要： Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current. The monitor unit includes a constant current source and a monitoring MOSFET formed on the same substrate as the plurality of MOSFETs, the substrate voltage regulating unit includes a comparison unit for comparing the source potential of the monitoring MOSFET with a predetermined reference potential with the drain terminal of the monitoring MOSFET and the drain terminals of the plurality of MOSFETs connected to the ground potential, and substrate voltage regulating unit feeds back the output voltage output based on the comparison result by the comparison unit to the substrate voltage of the monitoring MOSFET.

    Multichip module structure
    7.
    发明授权
    Multichip module structure 失效
    多芯片模块结构

    公开(公告)号：US06833626B2

    公开(公告)日：2004-12-21

    申请号：US10189549

    申请日：2002-07-08

    申请人： Jun Kajiwara ,  Masayoshi Kinoshita ,  Shiro Sakiyama

    发明人： Jun Kajiwara ,  Masayoshi Kinoshita ,  Shiro Sakiyama

    IPC分类号： H01L2940

    CPC分类号： H01L25/16 ,  G01R31/2853 ,  G01R31/318513 ,  H01L27/10897 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/3011 ,  H01L2224/05599

    摘要： A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

    摘要翻译： 大芯片包括从第一干线导线分支并延伸到相应导线的第一组支线，以便连接到相应的接合焊盘。 第一组的每条分支线包括连接控制元件和电阻器。 小芯片包括从第二干线分支的第二组支线，并延伸到相应的导线，以便连接到相应的接合焊盘。 第二组的每条分支线包括连接控制元件和电阻器。 通过在对第一和第二测试焊盘施加电压时测量电流值来确定接合焊盘之间是否正确地进行连接。

    Highly Sensitive Photo-Sensing Element and Photo-Sensing Device Using the Same
    9.
    发明申请
    Highly Sensitive Photo-Sensing Element and Photo-Sensing Device Using the Same 有权
    高灵敏感光元件和使用它的感光元件

    公开(公告)号：US20120068287A1

    公开(公告)日：2012-03-22

    申请号：US13236338

    申请日：2011-09-19

    申请人： Mitsuharu Tai ,  Hideo Sato ,  Mutsuko Hatano ,  Masayoshi Kinoshita

    发明人： Mitsuharu Tai ,  Hideo Sato ,  Mutsuko Hatano ,  Masayoshi Kinoshita

    IPC分类号： H01L31/0224

    CPC分类号： H01L27/1214 ,  G09G2360/14 ,  H01L31/1136

    摘要： According to the present invention, a highly sensitive photo-sensing element and a sensor driver circuit are prepared by planer process on an insulating substrate by using only polycrystalline material. Both the photo-sensing element and the sensor driver circuit are made of polycrystalline silicon film. As the photo-sensing element, a photo transistor is formed by using TFT, which comprises a first electrode 11 prepared on an insulating substrate 10, a photoelectric conversion region 14 and a second electrode 12, and a third electrode 13 disposed above the photoelectric conversion region 14. An impurity layer positioned closer to an intrinsic layer (density of active impurities is 1017 cm−3 or lower) is provided on the regions 15 and 16 on both sides under the third electrode 13 or on one of the regions 15 or 16 on one side.

    摘要翻译： 根据本发明，通过仅使用多晶材料，通过平面法在绝缘基板上制备高灵敏度的感光元件和传感器驱动电路。 感光元件和传感器驱动电路都由多晶硅膜制成。 作为感光元件，通过使用TFT形成光电晶体管，该TFT包括在绝缘基板10上制备的第一电极11，光电转换区域14和第二电极12以及设置在光电转换器之上的第三电极13 在第三电极13下方的区域15和16上，或者在区域15或16中的一个区域上设置位于更接近本征层（活性杂质的密度为1017cm-3或更低）的杂质层。 在一边。

    Phase adjustment circuit
    10.
    发明授权
    Phase adjustment circuit 有权
    相位调整电路

    公开(公告)号：US08106691B2

    公开(公告)日：2012-01-31

    申请号：US13206182

    申请日：2011-08-09

    申请人： Kazuaki Sogawa ,  Masayoshi Kinoshita ,  Yuji Yamada

    发明人： Kazuaki Sogawa ,  Masayoshi Kinoshita ,  Yuji Yamada

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0996 ,  H03L7/23

    摘要： In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.

    摘要翻译： 在将双频时钟的频率除以获得50％的占空比时钟的相位调整电路中，具有相位反转功能的第一½分频电路产生相位分离的中间参考时钟，相位参考时钟 和相位调整时钟。 第一相位控制电路相对于相位参考时钟控制中间参考时钟的相位处于期望的相位状态。 第二相位控制电路将相位调整时钟的相位相对于中间参考时钟控制在期望的相位状态。 因此，当相位调整时钟被调整为与相位基准时钟相位近似时，即使由于时钟抖动而改变，这些时钟之间的相位差也可以被正确和稳定地确定。