-
公开(公告)号：US07640384B2
公开(公告)日：2009-12-29
申请号：US11903249
申请日：2007-09-20
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 在一个实施例中，提供了存储用于执行监视机制的功能的指令的存储器。 监视机制具有使处理器响应于事件退出休眠状态的第一逻辑，其中退出休眠状态包括恢复处理在休眠状态期间被处理器放弃的处理资源的控制。 所述监视机制具有第二逻辑，以在所述处理器退出所述睡眠状态之后禁用与竞争锁相关联的节点的监视。
-
12.发明授权Mechanism for processor power state aware distribution of lowest priority interrupt 有权处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07191349B2
公开(公告)日：2007-03-13
申请号：US10330622
申请日：2002-12-26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
-
13.发明授权Mechanism for processor power state aware distribution of lowest priority interrupts 失效处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07761720B2
公开(公告)日：2010-07-20
申请号：US11704760
申请日：2007-02-09
IPC分类号： G06F1/26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
-
14.发明申请公开(公告)号：US20090070510A1
公开(公告)日：2009-03-12
申请号：US11966356
申请日：2007-12-28
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
-
公开(公告)号：US08984199B2
公开(公告)日：2015-03-17
申请号：US10631522
申请日：2003-07-31
CPC分类号： G06F9/4812 , G06F9/544
摘要： According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.
摘要翻译： 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。
-
公开(公告)号：US07769938B2
公开(公告)日：2010-08-03
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
-
公开(公告)号：US07328293B2
公开(公告)日：2008-02-05
申请号：US11716377
申请日：2007-03-09
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 根据一个实施例，监视与竞争锁相关联的节点; 并且寻求有争议的锁的处理器进入休眠状态直到发生监视事件。
-
18.发明授权Processor selection for an interrupt based on willingness to accept the interrupt and on priority 有权处理器根据意愿接受中断和优先级中断进行选择公开(公告)号：US08032681B2
公开(公告)日：2011-10-04
申请号：US11966356
申请日：2007-12-28
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
-
公开(公告)号：US07213093B2
公开(公告)日：2007-05-01
申请号：US10608708
申请日：2003-06-27
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
-
公开(公告)号：US07117396B2
公开(公告)日：2006-10-03
申请号：US10029308
申请日：2001-12-28
申请人： Eshwari P. Komarla , Suresh Marisetty , Mani Ayyar , Andrew J. Fish , Mohan J. Kumar , Shivnandan D. Kaushik
发明人： Eshwari P. Komarla , Suresh Marisetty , Mani Ayyar , Andrew J. Fish , Mohan J. Kumar , Shivnandan D. Kaushik
IPC分类号： G06F11/00
CPC分类号： G06F11/0787 , G06F11/073
摘要： A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.
-
-
-
-
-
-
-
-
-
搜索结果
42 条记录 (耗时 0.029 秒)
