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公开(公告)号：US20070238271A1
公开(公告)日：2007-10-11
申请号：US11806862
申请日：2007-06-05
申请人： Shoichi Yamauchi , Yoshiyuki Hattori , Kyoko Okada
发明人： Shoichi Yamauchi , Yoshiyuki Hattori , Kyoko Okada
IPC分类号： H01L21/20
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.
摘要翻译： 具有SJ结构的半导体器件具有比电池区域的耐电压更高的耐受电压的周边区域。 在周边区域的半导体层中形成有包含第二导电型杂质的半导体上层和包含第一导电型杂质的半导体下层，该第一导电型杂质的浓度低于构成该单元区域组合的第一部分区域。 在半导体上层的表面上形成场氧化物层。
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12.发明申请公开(公告)号：US20070013412A1
公开(公告)日：2007-01-18
申请号：US11472547
申请日：2006-06-22
IPC分类号： H03K19/091
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semiconductor layer; a terminal contact semiconductor region on a surface portion of the terminal upper semiconductor layer adjacent to the cell region; an insulation layer on the terminal upper semiconductor layer having a first part adjacent to the cell region with a small thickness and a second part adjacent to the first part with a large thickness; and a conductive layer in the cell region and a part of the terminal region, the conductive layer extending from the cell region to the part of the terminal region beyond the first part of the insulation layer.
摘要翻译： 半导体器件包括：单元区域; 终端区域 下半导体层; 包括超级结结构的下半导体层上的中间半导体层; 中间半导体层上的端子上半导体层; 在所述端子上半导体层的与所述单元区域相邻的表面部分上的端子接触半导体区域; 端子上半导体层上的绝缘层具有邻近具有小厚度的单元区域的第一部分和与厚度较大的第一部分相邻的第二部分; 以及在所述单元区域和所述端子区域的一部分中的导电层，所述导电层从所述单元区域延伸到所述绝缘层的所述第一部分之外的所述端子区域的所述部分。
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公开(公告)号：US20050077572A1
公开(公告)日：2005-04-14
申请号：US10960286
申请日：2004-10-08
IPC分类号： H01L29/06 , H01L29/40 , H01L29/417 , H01L29/78 , H01L29/49
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/402 , H01L29/41741 , H01L29/7813
摘要： A device includes a center portion, and a periphery portion disposed around the center portion. The periphery portion includes a first semiconductor layer, an intermediate layer, a second semiconductor layer, an insulation layer and an electrode. The intermediate layer includes a periodic construction having a first region and a second region. The center portion includes a contact region. The electrode extends to the periphery portion to have an extension length of the electrode between the contact region and a periphery of the electrode. The extension length of the electrode is equal to or longer than one-eighth of a distance between the contact region and an outer periphery of the periodic construction.
摘要翻译： 装置包括中心部分和围绕中心部分设置的周边部分。 周边部分包括第一半导体层，中间层，第二半导体层，绝缘层和电极。 中间层包括具有第一区域和第二区域的周期性结构。 中心部分包括接触区域。 电极延伸到周边部分，以使得电极在接触区域和电极周边之间具有延伸长度。 电极的延伸长度等于或长于接触区域和周期性构造的外周之间的距离的八分之一。
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公开(公告)号：US07364980B2
公开(公告)日：2008-04-29
申请号：US11539441
申请日：2006-10-06
IPC分类号： H01L21/76
CPC分类号： C30B25/165 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/0634
摘要： Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y
摘要翻译： 在具有外延膜的沟槽的开口处的闭合被抑制，从而提高了沟槽中的填充形态。 一种制造半导体衬底的方法包括在硅衬底13的表面上生长外延层11的步骤，在该外延层中形成沟槽14的步骤，以及将沟槽14内部填充的步骤 外延膜12，其中通过将卤素气体混入硅源气体而制成的混合气体作为原料气体循环，用外延膜填充沟槽内部，当将卤化物气体的标准流量定义为Xslm时，膜 通过硅源气体的循环形成的外延膜的形成速度定义为Ymum / min，在沟槽的纵横比小于10的情况下，满足表达式Y <0.2X + 0.10，在 沟槽的纵横比在10以上且小于20的情况下，满足表达式Y <0.2X + 0.05，在沟槽的纵横比为20以上的情况下，表达式Y <0.2× 满意
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公开(公告)号：US20070082455A1
公开(公告)日：2007-04-12
申请号：US11539441
申请日：2006-10-06
IPC分类号： H01L21/76
CPC分类号： C30B25/165 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/0634
摘要： Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y
摘要翻译： 在具有外延膜的沟槽的开口处的闭合被抑制，从而提高了沟槽中的填充形态。 一种制造半导体衬底的方法包括在硅衬底13的表面上生长外延层11的步骤，在该外延层中形成沟槽14的步骤，以及将沟槽14内部填充的步骤 外延膜12，其中通过将卤素气体混入硅源气体而制成的混合气体作为原料气体循环，用外延膜填充沟槽内部，当将卤化物气体的标准流量定义为Xslm时，膜 通过硅源气体的循环形成的外延膜的形成速度定义为Ymum / min，在沟槽的纵横比小于10的情况下，满足表达式Y <0.2X + 0.10，在 沟槽的纵横比在10以上且小于20的情况下，满足表达式Y <0.2X + 0.05，在沟槽的纵横比为20以上的情况下，表达式Y <0.2× 满意
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公开(公告)号：US07170119B2
公开(公告)日：2007-01-30
申请号：US10549151
申请日：2004-08-20
IPC分类号： H01L29/72
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/7813
摘要： In a vertical type MOSFET device having a super junction structure, in which a N conductive type column region and a P conductive type column region are alternately aligned, regarding to a distance between a terminal end of an active region and a terminal end of a column region, the terminal end of the column region is disposed at a position, which is separated from the active region terminal end by a distance obtained by subtracting a half of a width of the N conductive type column region from a distance corresponding to a depth of the column region. Thus, an electric field concentration at a specific portion in a region facing a narrow side of the column structure is prevented so that a breakdown voltage of the vertical type MOSFET is improved.
摘要翻译： 在具有超结结构的垂直型MOSFET器件中，其中N导电型列区域和P导电型列区域交替排列，关于有源区域的末端和列的末端之间的距离 区域中，列区域的末端设置在与有源区域终端分离距离所获得的距离的位置处，所述距离从对应于N导电型列区域的深度的距离减去所述N导电型列区域的宽度的一半 列区域。 因此，防止了在列结构的窄边的区域中的特定部分处的电场浓度，从而提高了垂直型MOSFET的击穿电压。
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公开(公告)号：US20050221547A1
公开(公告)日：2005-10-06
申请号：US11094782
申请日：2005-03-31
IPC分类号： H01L29/06 , H01L21/20 , H01L21/205 , H01L21/336 , H01L21/338 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L29/0634 , H01L29/7811
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底中形成沟槽; 以及在包括沟槽的侧壁和底部的衬底上形成外延膜，使得外延膜填充在沟槽中。 形成外延膜的步骤包括在沟槽被外延膜填充之前的最后步骤。 最终步骤具有外延膜的形成条件，使得形成在沟槽的侧壁上的外延膜在沟槽的开口处的生长速率小于沟槽位置处的生长速率， 其比沟槽的开口更深。
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公开(公告)号：US20050133859A1
公开(公告)日：2005-06-23
申请号：US11012116
申请日：2004-12-16
CPC分类号： H01L29/7813 , G06F17/5068 , H01L29/0634
摘要： A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure to reach the multi-dimensional super junction structure, so that dispersions of an on-resistance of the semiconductor device can be reduced. When a position at which the group of trench gate electrodes is created is shifted in one direction, the size of an overlap area common to the group of trench gate electrodes and an n-type column changes. However, the group of trench gate electrodes is oriented in such a way that the changes in overlap-area size are minimized.
摘要翻译： 半导体器件被制造成包括设计成多维超结结构的耐压保证层和一组沟槽栅极电极，每个沟槽栅电极穿透与多维超结结构接触的体层以达到 多维超结结构，能够降低半导体装置的导通电阻的分散。 当形成沟槽栅电极组的位置在一个方向上移动时，沟槽栅电极组和n型列共同的重叠区域的尺寸改变。 然而，沟槽栅电极组被定向成使得重叠区域尺寸的变化最小化。
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19.发明授权公开(公告)号：US07811907B2
公开(公告)日：2010-10-12
申请号：US11528678
申请日：2006-09-28
IPC分类号： H01L29/78 , H01L29/12 , H01L21/336 , H01L21/205
CPC分类号： H01L29/7813 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/045 , H01L29/0634 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在硅衬底的主表面上形成沟槽; 在主表面和沟槽中形成第一外延膜; 以及在所述第一外延膜上形成第二外延膜。 形成第一外延膜的步骤具有第一外延膜的第一生长速率的第一工艺条件。 形成第二外延膜的步骤具有第二外延膜的第二生长速率的第二工艺条件。 第二增长率大于第一增长率。
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公开(公告)号：US07601603B2
公开(公告)日：2009-10-13
申请号：US11094782
申请日：2005-03-31
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L21/823487 , H01L29/0634 , H01L29/7811
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底中形成沟槽; 以及在包括沟槽的侧壁和底部的衬底上形成外延膜，使得外延膜填充在沟槽中。 形成外延膜的步骤包括在沟槽被外延膜填充之前的最后步骤。 最终步骤具有外延膜的形成条件，使得形成在沟槽的侧壁上的外延膜在沟槽的开口处的生长速率小于沟槽位置处的生长速率， 其比沟槽的开口更深。
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