公开(公告)号：US08593180B2

公开(公告)日：2013-11-26

申请号：US13418066

申请日：2012-03-12

Applicant: Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

Inventor： Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

IPC: H03K19/02

CPC classification number: H01L29/42364 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/78684

Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

Abstract translation: 电路包括包括栅极和石墨烯通道的负差分电阻（NDR）器件和调制栅极上的栅极电压的栅极电压源，使得通过石墨烯通道的电流呈现负的差分电阻。

公开(公告)号：US08455862B2

公开(公告)日：2013-06-04

申请号：US13562827

申请日：2012-07-31

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/775

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78684 ,  H01L51/0048

Abstract: A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.

Abstract translation: 半导体器件包括设置在基底上的碳层，设置在碳层的一部分上的栅极叠层，由碳层和衬底限定的第一腔，由碳层和衬底限定的第二腔，源 区域，包括设置在第一腔中的第一导电触点，漏区，包括设置在第二腔中的第二导电触点。

公开(公告)号：US08354309B2

公开(公告)日：2013-01-15

申请号：US13347014

申请日：2012-01-10

Applicant: Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

Inventor： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract translation: 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20120329193A1

公开(公告)日：2012-12-27

申请号：US13605107

申请日：2012-09-06

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L21/336

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract translation: 一种用于形成传感器的方法，包括在衬底中形成通道，在通道中形成牺牲层，形成具有设置在衬底上的第一介电层的传感器，设置在第一电介质层上的石墨烯层，以及设置在第二电介质层 在石墨烯层上，源区域，漏极区域和栅极区域，其中栅极区域设置在牺牲层上，从沟道去除牺牲层。

公开(公告)号：US20120299125A1

公开(公告)日：2012-11-29

申请号：US13568832

申请日：2012-08-07

Applicant: Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

公开(公告)号：US20120248502A1

公开(公告)日：2012-10-04

申请号：US13074878

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7781 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置在可以包括III-V半导体表面层（例如砷化镓（GaAs））和掩埋层（例如AlAs）的分层半导体晶片上限定FET基座。 介电材料，例如氧化铝（AlO），至少在FET源极/漏极区域中围绕基座。 导电盖帽在相对的通道端部封闭通道侧壁。 绝缘体上的III-V（IIIVOI）器件形成电介质材料层的厚度超过器件长度的一半。 源极/漏极触点形成到盖并终止在掩埋层中的介电材料之中/之上。

公开(公告)号：US20120175594A1

公开(公告)日：2012-07-12

申请号：US12986342

申请日：2011-01-07

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/15 ,  H01L21/336

CPC classification number: H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract translation: 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

公开(公告)号：US20120146001A1

公开(公告)日：2012-06-14

申请号：US13401967

申请日：2012-02-22

Applicant: Zhihong Chen ,  Dechao Guo ,  Shu-Jen Han ,  Kai Zhao

Inventor： Zhihong Chen ,  Dechao Guo ,  Shu-Jen Han ,  Kai Zhao

IPC: H01L29/78 ,  B82Y99/00

CPC classification number: H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78684

Abstract: A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.

Abstract translation: 碳基场效应晶体管（FET）包括基板; 位于所述基板上的碳层，所述碳层包括沟道区，以及位于所述沟道区两侧的源区和漏区; 位于所述碳层中的沟道区上的栅电极，所述栅电极包括第一电介质层，位于所述第一电介质层上的栅极金属层和位于所述栅极金属层上的氮化物层; 以及间隔件，其包括邻近所述栅电极的第二电介质层，其中所述间隔物不位于所述碳层上。

公开(公告)号：US20120032149A1

公开(公告)日：2012-02-09

申请号：US12850095

申请日：2010-08-04

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

Abstract translation: 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US20110227043A1

公开(公告)日：2011-09-22

申请号：US12727434

申请日：2010-03-19

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract translation: 一种用于形成传感器的方法，包括在衬底中形成通道，在通道中形成牺牲层，形成具有设置在衬底上的第一介电层的传感器，设置在第一电介质层上的石墨烯层，以及设置在第二电介质层 在石墨烯层上，源区域，漏极区域和栅极区域，其中栅极区域设置在牺牲层上，从沟道去除牺牲层。