公开(公告)号：US20210082516A1

公开(公告)日：2021-03-18

申请号：US16574059

申请日：2019-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/24

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.

公开(公告)号：US10943661B2

公开(公告)日：2021-03-09

申请号：US16550253

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20200349422A1

公开(公告)日：2020-11-05

申请号：US16449205

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stephen Trinh ,  Thuan Vu ,  Stanley Hong ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G11C16/08

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

公开(公告)号：US20200242460A1

公开(公告)日：2020-07-30

申请号：US16360733

申请日：2019-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C16/10

Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

公开(公告)号：US20200019849A1

公开(公告)日：2020-01-16

申请号：US16151259

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Thuan Vu ,  Anh Ly ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/063 ,  G06F3/06 ,  G06F11/16

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

公开(公告)号：US20190341110A1

公开(公告)日：2019-11-07

申请号：US16042972

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Staniey Hong ,  Anh Ly ,  Vlpln Tlwarl ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L29/788 ,  H01L27/11521

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US10340010B2

公开(公告)日：2019-07-02

申请号：US15238681

申请日：2016-08-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/32

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US10325666B2

公开(公告)日：2019-06-18

申请号：US16218398

申请日：2018-12-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C5/14 ,  G11C16/10 ,  G11C8/08 ,  G11C16/16

Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

公开(公告)号：US10216242B2

公开(公告)日：2019-02-26

申请号：US15610612

申请日：2017-05-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Anh Ly ,  Hung Quoc Nguyen

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/28 ,  G11C7/20 ,  G11C16/30 ,  H03K19/0185 ,  G11C11/4074

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.

公开(公告)号：US20180144804A1

公开(公告)日：2018-05-24

申请号：US15873872

申请日：2018-01-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28 ,  G11C16/24 ,  G11C7/06 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/24

Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.