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公开(公告)号：US08959270B2
公开(公告)日：2015-02-17
申请号：US12962146
申请日：2010-12-07
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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12.发明授权DMA controller which performs DMA assist for one peripheral interface controller and DMA operation for another peripheral interface controller 有权DMA控制器为一个外设接口控制器执行DMA辅助，并为另一个外设接口控制器执行DMA操作公开(公告)号：US08417844B2
公开(公告)日：2013-04-09
申请号：US13474373
申请日：2012-05-17
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。
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公开(公告)号：US20120144172A1
公开(公告)日：2012-06-07
申请号：US12962146
申请日：2010-12-07
IPC分类号： G06F9/38
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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公开(公告)号：US07624235B2
公开(公告)日：2009-11-24
申请号：US11565391
申请日：2006-11-30
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译： 在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。
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公开(公告)号：US20090055568A1
公开(公告)日：2009-02-26
申请号：US12263255
申请日：2008-10-31
IPC分类号： G06F13/14
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。
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公开(公告)号：US20080126606A1
公开(公告)日：2008-05-29
申请号：US11523330
申请日：2006-09-19
申请人： James Wang , Choon Ping Chng , Mark D. Hayter , Ruchi Wadhawan
发明人： James Wang , Choon Ping Chng , Mark D. Hayter , Ruchi Wadhawan
IPC分类号： G06F3/00
CPC分类号： H04L47/10 , G06F13/28 , G06F13/385 , H04L47/39
摘要： In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.
摘要翻译： 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。
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公开(公告)号：US20070162652A1
公开(公告)日：2007-07-12
申请号：US11682065
申请日：2007-03-05
申请人： Dominic Go , Mark Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。
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18.发明授权Detecting valid data patterns for adapting equalization gain and offset for data transmissions 失效检测有效数据模式，以适应数据传输的均衡增益和偏移量公开(公告)号：US06222876B1
公开(公告)日：2001-04-24
申请号：US08994866
申请日：1997-12-19
申请人： Ryan E. Hirth , Ruchi Wadhawan
发明人： Ryan E. Hirth , Ruchi Wadhawan
IPC分类号： H04B346
CPC分类号： H04L25/03885
摘要： A method for tuning an adaptive equalizer in order to receive digital signals from a transmission medium both coarse and fine tuning methods to adaptively equalize a signal received from the transmission medium. The coarse tuning method adjusts an equalizer such that the post equalized signal starts to resemble a known data pattern, such as an MLT3 data pattern. The coarse tuning method monitors and corrects for several things: illegal transitions, over equalization, statistical data pattern anomalies and saturation conditions. Fine tuning methods operate concurrently with the coarse tuning methods and function from the point at which the coarse tuning methods stop being efficient. Additionally, the fine tuning methods hold the waveform locked in. In addition to coarse tuning and fine tuning of the equalizer, the present invention also adjusts gain of the overall signal such that the post equalized signal is always a certain amplitude. It also corrects for offsets that may get superimposed on the signal as it passes through the receive channel and which may lead to erroneous bit decisions. The method is applicable to a variety of data communication standards including 100 Base-X, FDDI and ATM-155.
摘要翻译： 一种用于调谐自适应均衡器以便从传输介质接收数字信号的方法，用于粗调和微调方法以自适应均衡从传输介质接收的信号。 粗调方法调整均衡器，使得后均衡信号开始类似于已知数据模式，例如MLT3数据模式。 粗调方法监视和纠正以下几件事情：非法转换，过均衡，统计数据模式异常和饱和条件。 微调方法与粗调方法和功能从粗调方式停止有效的角度同时运行。 此外，微调方法保持波形锁定。除了均衡器的粗调和微调外，本发明还调整总体信号的增益，使得后均衡信号总是一定的幅度。 它还可以纠正在信号通过接收通道时可能会叠加在信号上的偏移量，并可能导致错误的位决定。 该方法适用于各种数据通信标准，包括100 Base-X，FDDI和ATM-155。
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公开(公告)号：US20120297097A1
公开(公告)日：2012-11-22
申请号：US13566485
申请日：2012-08-03
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。
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公开(公告)号：US20120167107A1
公开(公告)日：2012-06-28
申请号：US13413796
申请日：2012-03-07
IPC分类号： G06F9/46
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。
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