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公开(公告)号：US08959270B2
公开(公告)日：2015-02-17
申请号：US12962146
申请日：2010-12-07
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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公开(公告)号：US20120144172A1
公开(公告)日：2012-06-07
申请号：US12962146
申请日：2010-12-07
IPC分类号： G06F9/38
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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公开(公告)号：US20120167107A1
公开(公告)日：2012-06-28
申请号：US13413796
申请日：2012-03-07
IPC分类号： G06F9/46
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。
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4.发明授权Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state 有权在接收到改变性能状态的请求时，根据性能状态表来修改多个电路中的性能参数公开(公告)号：US08468373B2
公开(公告)日：2013-06-18
申请号：US13006967
申请日：2011-01-14
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译： 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在一些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。
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公开(公告)号：US20120185703A1
公开(公告)日：2012-07-19
申请号：US13006967
申请日：2011-01-14
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译： 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在一些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。
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公开(公告)号：US08332559B2
公开(公告)日：2012-12-11
申请号：US13413796
申请日：2012-03-07
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。
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公开(公告)号：US08156275B2
公开(公告)日：2012-04-10
申请号：US12465182
申请日：2009-05-13
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
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公开(公告)号：US20100293401A1
公开(公告)日：2010-11-18
申请号：US12465182
申请日：2009-05-13
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。
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9.发明授权Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements 有权中断控制器中的原子中断屏蔽，以防止传递相同的中断向量用于连续的中断确认公开(公告)号：US08458386B2
公开(公告)日：2013-06-04
申请号：US12962089
申请日：2010-12-07
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812 , G06F9/52
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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10.发明授权公开(公告)号：US08443216B2
公开(公告)日：2013-05-14
申请号：US13590217
申请日：2012-08-21
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
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