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公开(公告)号：US08959270B2
公开(公告)日：2015-02-17
申请号：US12962146
申请日：2010-12-07
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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公开(公告)号：US20120144172A1
公开(公告)日：2012-06-07
申请号：US12962146
申请日：2010-12-07
IPC分类号： G06F9/38
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译： 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。
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公开(公告)号：US20120185703A1
公开(公告)日：2012-07-19
申请号：US13006967
申请日：2011-01-14
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译： 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在一些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。
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4.发明授权Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state 有权在接收到改变性能状态的请求时，根据性能状态表来修改多个电路中的性能参数公开(公告)号：US08468373B2
公开(公告)日：2013-06-18
申请号：US13006967
申请日：2011-01-14
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译： 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在一些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。
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公开(公告)号：US08799715B2
公开(公告)日：2014-08-05
申请号：US13533295
申请日：2012-06-26
申请人： Manu Gulati , James D. Ramsay , Erik P. Machnicki , Jianlin Yu
发明人： Manu Gulati , James D. Ramsay , Erik P. Machnicki , Jianlin Yu
IPC分类号： G06F11/00
CPC分类号： G06F11/27
摘要： In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.
摘要翻译： 在一个实施例中，SOC包括多个组件，包括CPU复合体和一个或多个非CPU组件，例如外围接口控制器，存储器控制器，媒体组件等.SAC还包括SOC调试控制单元，其被耦合以接收 从组件检测到调试事件。 每个组件可以包括本地调试控制单元，其被配置为监视该组件内的各种调试事件。 调试事件可能是组件特有的。 本地调试控制单元可以将检测到的事件发送到SOC调试控制单元。 SOC调试控制单元可以从一个或多个组件检测一个或多个事件，并且可以响应于检测所选择的事件而停止SOC的组件。
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6.发明申请公开(公告)号：US20120144224A1
公开(公告)日：2012-06-07
申请号：US12960708
申请日：2010-12-06
IPC分类号： G06F1/08
摘要： Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.
摘要翻译： 调整设备时钟的时钟源以减少设备内的无线通信（例如射频（RF））干扰。 设备时钟可以从例如耦合到显示器的串行接口的输入时钟导出，并且可以最初由第一时钟驱动。 之后，可以确定串行接口时钟是或将会干扰无线通信。 因此，在修改第一时钟的同时，可以将临时时钟信号提供给设备时钟。 一旦被修改，修改的时钟信号可以被提供给设备时钟以减少无线通信干扰。
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7.发明申请METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING 失效使用基于DEADLINE的调度在多芯片系统中执行DMA的方法和系统公开(公告)号：US20100005470A1
公开(公告)日：2010-01-07
申请号：US12167096
申请日：2008-07-02
IPC分类号： G06F9/46
摘要： A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.
摘要翻译： 直接存储器访问（DMA）引擎根据分配的传送优先级和完成传送的截止时间调度片上系统数据处理系统的数据传输请求。 转移优先级基于表示错过期限的惩罚的硬度。 优先权也被分配到零期限转移请求，其中有罚款，无论传输完成的时间早。 如果需要，可以根据优先级按照时间表调度传输请求，以便限制较低优先级请求的延迟，具有最高优先级的硬实时传输，其中丢失最后期限的惩罚是最大的时间片。 在进行当前事务处理以最大效率的情况下，会发布准备下一次数据传输的服务请求。 当接收到更高的紧急请求时，可以抢占当前的传输。
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公开(公告)号：US07249202B2
公开(公告)日：2007-07-24
申请号：US10899196
申请日：2004-07-26
申请人： Moshe B. Simon , Erik P. Machnicki , Mark Longley
发明人： Moshe B. Simon , Erik P. Machnicki , Mark Longley
CPC分类号： G06F7/49921 , G06F7/49994 , G06F7/505 , G06F7/523 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F2207/382 , G06F2207/3828
摘要： A method and system for DMA transfer of data in scatter/gather mode. A table of buffer descriptors may be used to determine the next buffer to be used when a current buffer storing data that has been transferred or will be transferred and may be used in automatic buffer switching, which does not require processor intervention. Entries in the table of buffer descriptors are entered programmatically. The method and system also provide for hardware writing to table of packet descriptors which describes location and size of incoming data and can indicate whether a packet of data straddles two or more buffers, thus decoupling packet sizes from buffer sizes.
摘要翻译： 用于以分散/收集模式DMA传输数据的方法和系统。 可以使用缓冲器描述符表来确定当存储已被传送或将被传送的数据的当前缓冲器时使用的下一个缓冲器，并且可以用于不需要处理器干预的自动缓冲器切换。 缓冲区描述符表中的条目以编程方式输入。 该方法和系统还提供对描述入站数据的位置和大小的分组描述符的表的硬件写入，并且可以指示数据包是否跨越两个或更多个缓冲器，从而将分组大小与缓冲器大小分离。
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9.发明授权公开(公告)号：US08645743B2
公开(公告)日：2014-02-04
申请号：US12951788
申请日：2010-11-22
申请人： Erik P. Machnicki , Hao Chen , Sanjay Mansingh
发明人： Erik P. Machnicki , Hao Chen , Sanjay Mansingh
IPC分类号： G06F1/00
CPC分类号： H03L7/07 , H03L7/0814
摘要： An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.
摘要翻译： 在频率变化期间，有效的延迟锁定环（DLL）训练协议包括具有包含主DLL和从属DLL的存储器物理层（PHY）单元的集成电路。 主DLL可以将第一参考时钟延迟一定量，并提供对应于延迟量的参考延迟值。 从属DLL可以基于接收的配置延迟值将第二参考时钟延迟第二量。 接口单元可以基于参考延迟值生成配置延迟值。 功率管理单元可以提供第二参考时钟的频率正在改变的指示。 响应于接收到指示，接口单元可以使用预定的缩放值来生成对应于新频率的新的配置延迟值，并向存储器PHY单元提供新的配置延迟值。
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公开(公告)号：US20130346800A1
公开(公告)日：2013-12-26
申请号：US13533295
申请日：2012-06-26
申请人： Manu Gulati , James D. Ramsay , Erik P. Machnicki , Jianlin Yu
发明人： Manu Gulati , James D. Ramsay , Erik P. Machnicki , Jianlin Yu
IPC分类号： G06F11/273
CPC分类号： G06F11/27
摘要： In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.
摘要翻译： 在一个实施例中，SOC包括多个组件，包括CPU复合体和一个或多个非CPU组件，例如外围接口控制器，存储器控制器，媒体组件等.SAC还包括SOC调试控制单元，其被耦合以接收 从组件检测到调试事件。 每个组件可以包括本地调试控制单元，其被配置为监视该组件内的各种调试事件。 调试事件可能是组件特有的。 本地调试控制单元可以将检测到的事件发送到SOC调试控制单元。 SOC调试控制单元可以从一个或多个组件检测一个或多个事件，并且可以响应于检测所选择的事件而停止SOC的组件。
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