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    Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography
    12.
    发明申请
    Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography 有权
    包含形成减少STI地形的通道半导体合金的半导体器件

    公开(公告)号：US20120156846A1

    公开(公告)日：2012-06-21

    申请号：US13191993

    申请日：2011-07-27

    申请人： Hans-Juergen Thees ,  Stephan Kronholz ,  Maciej Wiatr

    发明人： Hans-Juergen Thees ,  Stephan Kronholz ,  Maciej Wiatr

    IPC分类号： H01L21/8234 ,  H01L21/76

    CPC分类号： H01L21/823807 ,  H01L21/76232 ,  H01L21/823878

    摘要： In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.

    摘要翻译： 在复杂的半导体器件中，半导体合金，例如硅/锗形式的阈值调节半导体材料，可以在早期制造阶段中选择性地在某些活性区域中提供，其中明显的凹陷程度和材料损失 在隔离区域中，可以通过在隔离区域上选择性地提供保护材料层来避免。 例如，在一些说明性实施例中，硅材料可以选择性地沉积在隔离区域上。

    NFET Device with Tensile Stressed Channel Region and Methods of Forming Same
    14.
    发明申请
    NFET Device with Tensile Stressed Channel Region and Methods of Forming Same 审中-公开
    具有拉伸强度通道区域的NFET器件及其形成方法相同

    公开(公告)号：US20130175577A1

    公开(公告)日：2013-07-11

    申请号：US13346299

    申请日：2012-01-09

    申请人： Chung Foong Tan ,  Maciej Wiatr ,  Stephan Kronholz

    发明人： Chung Foong Tan ,  Maciej Wiatr ,  Stephan Kronholz

    IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/66651

    摘要： Disclosed herein is an NFET device with a tensile stressed channel region and various methods of making such an NFET device. In one example, the NFET transistor includes a semiconducting substrate, a first layer of semiconductor material positioned above the substrate, a second capping layer of semiconductor material positioned above the first layer of semiconductor material and a gate electrode structure positioned above the second capping layer of semiconductor material.

    摘要翻译： 本文公开了具有拉伸应力通道区域的NFET器件和制造这种NFET器件的各种方法。 在一个示例中，NFET晶体管包括半导体衬底，位于衬底上方的第一半导体材料层，位于第一半导体材料层上方的半导体材料的第二覆盖层和位于第二覆盖层上方的栅电极结构 半导体材料。

    Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation
    17.
    发明授权
    Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation 有权
    通过在阱注入之前形成凹槽来提高通道半导体合金的沉积均匀性

    公开(公告)号：US08722486B2

    公开(公告)日：2014-05-13

    申请号：US12908053

    申请日：2010-10-20

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

    摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

    摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。

    Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor
    19.
    发明申请
    Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor 审中-公开
    形成面应力诱导应力的方法近似于晶体管的栅极结构

    公开(公告)号：US20130175585A1

    公开(公告)日：2013-07-11

    申请号：US13348184

    申请日：2012-01-11

    申请人： Chung Foong Tan ,  Maciej Wiatr ,  Stephan Kronholz ,  Falong Zhou ,  Ying Hao Hsieh

    发明人： Chung Foong Tan ,  Maciej Wiatr ,  Stephan Kronholz ,  Falong Zhou ,  Ying Hao Hsieh

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/1054 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7848

    摘要： Disclosed herein are various methods of forming faceted stress-inducing stressors proximate the gate structure of a transistor. In one example, a method includes forming a first recess in an active region of a semiconducting substrate, forming a first semiconductor material in the first recess and forming a gate structure above the first semiconductor material. In this example, the method includes the additional steps of performing a crystalline orientation-dependent etching process on the first semiconductor material to define a plurality of second recesses proximate the gate structure, wherein each of the second recesses has a faceted edge, and forming a first region of stress-inducing semiconductor material in each of the second recesses, wherein each of the first regions of stress-inducing semiconductor material has a faceted edge that engages a corresponding faceted edge in one of the second recesses.

    摘要翻译： 本文公开了在晶体管的栅极结构附近形成面应力诱导应力源的各种方法。 在一个示例中，一种方法包括在半导体衬底的有源区中形成第一凹槽，在第一凹槽中形成第一半导体材料，并在第一半导体材料之上形成栅极结构。 在该示例中，该方法包括对第一半导体材料执行结晶取向依赖蚀刻工艺以限定靠近栅极结构的多个第二凹槽的附加步骤，其中每个第二凹槽具有刻面边缘，并且形成 在每个第二凹部中的应力诱导半导体材料的第一区域，其中所述第一应力诱导半导体材料区域中的每一个具有与所述第二凹部中的一个凹部中的相应的刻面边缘接合的刻面边缘。