公开(公告)号：US07109746B1

公开(公告)日：2006-09-19

申请号：US10806697

申请日：2004-03-22

申请人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

发明人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/1776

摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

摘要翻译： 描述用于错误检测的数据监视的方法和装置。 可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。 功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。 主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。 辅助地址线耦合到与功能发生器相关联的存储器单元组。 掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

公开(公告)号：US6033938A

公开(公告)日：2000-03-07

申请号：US751193

申请日：1996-11-15

申请人： Martin L. Voogel ,  Yakov Karpovich ,  Michael J. Hart

发明人： Martin L. Voogel ,  Yakov Karpovich ,  Michael J. Hart

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： Treatment of the positive electrode interface of an antifuse provides significantly improved on-state reliability. Treatments include, but are not limited to, a plasma etch using carbon tetrafluoride (CF.sub.4), a sputter clean using Argon, and wet chemical treatments using dimethyl formamide (and water) or a resist developer.

摘要翻译： 反熔丝的正极接口的处理提供了显着改善的导通状态可靠性。 处理包括但不限于使用四氟化碳（CF4）的等离子体蚀刻，使用氩气的溅射清洁以及使用二甲基甲酰胺（和水）或抗蚀剂显影剂的湿化学处理。

公开(公告)号：US07376000B1

公开(公告)日：2008-05-20

申请号：US11503694

申请日：2006-08-14

申请人： Martin L. Voogel ,  Steven P. Young

发明人： Martin L. Voogel ,  Steven P. Young

IPC分类号： G11C11/24

CPC分类号： G11C11/4125 ,  H03K19/177

摘要： Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

摘要翻译： 将金属 - 金属电容器添加到静态存储器单元中以减少对SEU的敏感性的结构和方法。 金属对金属电容器的添加特别适用于可编程逻辑器件（PLD），因为实现有效的金属对金属电容器所需的面积比较大（例如）与静态存储器的尺寸相比较 细胞本身 PLD的配置存储器单元通常放置在可被金属对金属电容器覆盖的其它逻辑（例如由配置存储器单元控制的可配置元件）旁边。 因此，可以在PLD配置存储单元中使用金属对金属电容器，其中它们在简单的存储器阵列中可能是不切实际的。 然而，金属对金属电容器也可以应用于除PLD之外的集成电路。

公开(公告)号：US07064574B1

公开(公告)日：2006-06-20

申请号：US10864254

申请日：2004-06-08

申请人： Martin L. Voogel ,  Steven P. Young

发明人： Martin L. Voogel ,  Steven P. Young

IPC分类号： H03K19/003

CPC分类号： H03K19/1776 ,  H03K3/0375 ,  H03K19/17764 ,  H03K19/1778

摘要： Structures and methods of reducing the susceptibility of programmable logic device (PLD) configuration memory cells to single event upsets (SEUs) by selectively adding metal-to-metal capacitors thereto. By adding capacitance to storage nodes in a memory cell, the susceptibility of the memory cell to SEUs is reduced. However, the performance of the memory cell also suffers. In PLD configuration memory cells, performance is not the most important factor. Therefore, for example, SEU-reducing capacitors can be selectively added to the PLD configuration memory cells while omitting the capacitors from user storage elements (e.g., block RAM) within the PLD. Thus, performance of the user storage elements is not adversely affected. Further, the use of metal-to-metal capacitors is well-suited to the configuration memory cells of a PLD, because these memory cells typically have additional area available for the capacitors above the programmable logic elements controlled by the associated configuration memory cells.

摘要翻译： 通过选择性地向其中添加金属对金属电容器，将可编程逻辑器件（PLD）配置存储单元的易感性降低到单事件扰乱（SEU）的结构和方法。 通过向存储器单元中的存储节点增加电容，减少了存储器单元对SEU的敏感性。 然而，存储单元的性能也会受到影响。 在PLD配置存储单元中，性能不是最重要的因素。 因此，例如，可以在PLD中的用户存储元件（例如，块RAM）省略电容器的同时，将选择性地将SEU减小电容器添加到PLD配置存储单元。 因此，用户存储元件的性能不会受到不利影响。 此外，使用金属对金属电容器非常适合于PLD的配置存储器单元，因为这些存储器单元通常具有可用于由相关配置存储器单元控制的可编程逻辑元件之上的电容器的附加区域。

公开(公告)号：US07110281B1

公开(公告)日：2006-09-19

申请号：US10864240

申请日：2004-06-08

申请人： Martin L. Voogel ,  Steven P. Young

发明人： Martin L. Voogel ,  Steven P. Young

IPC分类号： G11C11/24

CPC分类号： G11C11/4125 ,  H03K19/177

摘要： Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

摘要翻译： 将金属 - 金属电容器添加到静态存储器单元以减少对SEU的敏感性的结构和方法。 金属对金属电容器的添加特别适用于可编程逻辑器件（PLD），因为实现有效的金属对金属电容器所需的面积比较大（例如）与静态存储器的尺寸相比较 细胞本身 PLD的配置存储器单元通常放置在可被金属对金属电容器覆盖的其它逻辑（例如由配置存储器单元控制的可配置元件）旁边。 因此，可以在PLD配置存储单元中使用金属对金属电容器，其中它们在简单的存储器阵列中可能是不切实际的。 然而，金属对金属电容器也可以应用于除PLD之外的集成电路。

公开(公告)号：US06438065B1

公开(公告)日：2002-08-20

申请号：US09552280

申请日：2000-04-19

申请人： Kameswara K. Rao ,  Martin L. Voogel ,  Michael J. Hart

发明人： Kameswara K. Rao ,  Martin L. Voogel ,  Michael J. Hart

IPC分类号： G11C800

CPC分类号： G11C16/08

摘要： A field programmable gate array (FPGA) includes a first non-volatile memory cell and a second non-volatile memory cell. Each of the two non-volatile memory cells is capable of storing at least one bit of information. The second non-volatile memory cell provides redundant storage of the information stored in the first non-volatile memory cell. A read circuit is coupled to the first non-volatile memory cell and the second non-volatile memory cell. The read circuit simultaneously reads the information stored in the first and second non-volatile memory cells, The read circuit reads the information stored in the first non-volatile memory cell even if the second non-volatile memory cell is defective or is not programmed properly. The FPGA may include a third non-volatile memory cell coupled to the read circuit, which provides redundant storage of the information stored in the first non-volatile memory cell. Each non-volatile memory cell includes a storage transistor having a source and a drain, both of which are coupled to ground. Additionally, each storage transistor has a gate oxide. Each non-volatile memory cell is programmed by breaking the gate oxide of the storage transistor.

摘要翻译： 现场可编程门阵列（FPGA）包括第一非易失性存储单元和第二非易失性存储单元。 两个非易失性存储器单元中的每一个能够存储至少一个位的信息。 第二非易失性存储单元提供存储在第一非易失性存储单元中的信息的冗余存储。 读取电路耦合到第一非易失性存储单元和第二非易失性存储单元。 读取电路同时读取存储在第一和第二非易失性存储单元中的信息。即使第二非易失性存储器单元有缺陷或未正确编程，读取电路读取存储在第一非易失性存储器单元中的信息 。 FPGA可以包括耦合到读取电路的第三非易失性存储器单元，其提供存储在第一非易失性存储器单元中的信息的冗余存储。 每个非易失性存储单元包括具有源极和漏极的存储晶体管，二者都耦合到地。 另外，每个存储晶体管具有栅极氧化物。 通过断开存储晶体管的栅极氧化物来对每个非易失性存储单元进行编程。

公开(公告)号：US06243294B1

公开(公告)日：2001-06-05

申请号：US09552625

申请日：2000-04-19

申请人： Kameswara K. Rao ,  Martin L. Voogel ,  Michael J. Hart

发明人： Kameswara K. Rao ,  Martin L. Voogel ,  Michael J. Hart

IPC分类号： G11C1604

CPC分类号： G11C16/08

摘要： A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. The second signal line applies a positive voltage to the memory cells when programming a memory cell outside the row of memory cells. Each memory cell is a one-time programmable non-volatile memory cell. Each memory cell includes a storage transistor and an access transistor coupled to one another. The memory cell can be programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third signal line coupled to the memory cell and extending parallel to the word line. A programming voltage is applied to the selected bit line to program the memory cell.

摘要翻译： 现场可编程门阵列（FPGA）包含存储单元阵列。 字线耦合到阵列中的一行存储器单元。 第二信号线耦合到该行存储器单元并且与字线并行延伸。 当对存储器单元行中的存储单元进行编程时，第二信号线向存储器单元施加零电压。 当对存储器单元行之外的存储单元进行编程时，第二信号线向存储器单元施加正电压。 每个存储单元是一次性可编程非易失性存储单元。 每个存储单元包括彼此耦合的存储晶体管和存取晶体管。 可以通过选择与被编程的存储器单元相关联的字线和位线来对存储器单元进行编程。 零电压被施加到耦合到存储器单元并平行于字线延伸的第三信号线。 将编程电压施加到所选位线以对存储器单元进行编程。

公开(公告)号：US07301796B1

公开(公告)日：2007-11-27

申请号：US11503588

申请日：2006-08-14

申请人： Martin L. Voogel ,  Steven P. Young

发明人： Martin L. Voogel ,  Steven P. Young

IPC分类号： G11C11/24

CPC分类号： G11C11/4125 ,  H03K19/177

摘要： Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

摘要翻译： 将金属 - 金属电容器添加到静态存储器单元中以减少对SEU的敏感性的结构和方法。 金属对金属电容器的添加特别适用于可编程逻辑器件（PLD），因为实现有效的金属对金属电容器所需的面积比较大（例如）与静态存储器的尺寸相比较 细胞本身 PLD的配置存储器单元通常放置在可被金属对金属电容器覆盖的其它逻辑（例如由配置存储器单元控制的可配置元件）旁边。 因此，可以在PLD配置存储单元中使用金属对金属电容器，其中它们在简单的存储器阵列中可能是不切实际的。 然而，金属对金属电容器也可以应用于除PLD之外的集成电路。

公开(公告)号：US06549458B1

公开(公告)日：2003-04-15

申请号：US10040044

申请日：2001-10-25

申请人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

发明人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC分类号： G11C1400

CPC分类号： G11C16/08

摘要： Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

摘要翻译： 用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。 有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

公开(公告)号：US06522582B1

公开(公告)日：2003-02-18

申请号：US09553571

申请日：2000-04-19

申请人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

发明人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC分类号： G11C1400

CPC分类号： G11C16/08

摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

摘要翻译： 描述了用于非易失性存储器件的存储单元结构和相关电路。 可以使用标准CMOS工艺制造电池结构，例如 次0.35微米或次级0.25微米工艺。 优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。 有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。 例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径 型源极/漏极区域。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。 此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。 这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。