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    3-dimensional NOR strings with segmented shared source regions
    12.
    发明授权
    3-dimensional NOR strings with segmented shared source regions 有权

    公开(公告)号：US11335693B2

    公开(公告)日：2022-05-17

    申请号：US17170664

    申请日：2021-02-08

    Applicant: Sunrise Memory Corporation

    Inventor： Eli Harari ,  Raul Adrian Cernea

    IPC: G11C7/18 ,  H01L27/11 ,  H01L27/11578 ,  H03K19/20 ,  H03K19/1776 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786

    Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

    3-Dimensional NOR Strings with Segmented Shared Source Regions
    14.
    发明申请
    3-Dimensional NOR Strings with Segmented Shared Source Regions 有权

    公开(公告)号：US20210233926A1

    公开(公告)日：2021-07-29

    申请号：US17170664

    申请日：2021-02-08

    Applicant: Sunrise Memory Corporation

    Inventor： Eli Harari ,  Raul Adrian Cernea

    IPC: H01L27/11578 ,  G11C7/18 ,  H03K19/20 ,  H03K19/1776 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

    3-Dimensional NOR Strings with Segmented Shared Source Regions
    17.
    发明申请
    3-Dimensional NOR Strings with Segmented Shared Source Regions 审中-公开

    公开(公告)号：US20180366485A1

    公开(公告)日：2018-12-20

    申请号：US16006612

    申请日：2018-06-12

    Applicant: Sunrise Memory Corporation

    Inventor： Eli Harari ,  Raul Adrian Cernea

    IPC: H01L27/11578 ,  G11C7/18 ,  G11C16/04 ,  H03K19/20 ,  H03K19/177

    Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

    Memory Device Including Arrangement of Independently And Concurrently Operable Tiles of Memory Transistors
    20.
    发明公开
    Memory Device Including Arrangement of Independently And Concurrently Operable Tiles of Memory Transistors 审中-公开

    公开(公告)号：US20230187413A1

    公开(公告)日：2023-06-15

    申请号：US18059974

    申请日：2022-11-29

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Masahiro Yoshihara ,  Tz-Yi Liu ,  Raul Adrian Cernea ,  Shay Fux ,  Sagie Goldenberg ,  Eli Harari

    IPC: H01L25/065 ,  H01L25/18

    CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/06541

    Abstract: In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.

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