SEMICONDUCTOR DEVICE HAVING STACKED TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STACKED TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    具有堆叠晶体管的半导体器件及其制造方法

    公开(公告)号:US20070181957A1

    公开(公告)日:2007-08-09

    申请号:US11670946

    申请日:2007-02-02

    CPC classification number: H01L27/0688 H01L21/8221

    Abstract: Provided is a semiconductor device including a thin film transistor with at least one protruding impurity region and a method for manufacturing the same. The semiconductor device includes bulk transistors formed on a semiconductor substrate and an interlayer insulation layer covering the bulk transistor. At least one thin film transistor is formed on the interlayer insulation layer including impurity regions adjacent thereto. At least one impurity region of the thin film transistor protrudes higher than the other impurity region.

    Abstract translation: 提供一种包括具有至少一个突出杂质区的薄膜晶体管的半导体器件及其制造方法。 半导体器件包括形成在半导体衬底上的体晶体管和覆盖本体晶体管的层间绝缘层。 在包括与其相邻的杂质区域的层间绝缘层上形成至少一个薄膜晶体管。 薄膜晶体管的至少一个杂质区域比其他杂质区域突出。

    PHOTO MASK SET FOR FORMING MULTI-LAYERED INTERCONNECTION LINES AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME
    12.
    发明申请
    PHOTO MASK SET FOR FORMING MULTI-LAYERED INTERCONNECTION LINES AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME 有权
    用于形成多层互连线的照相遮罩和使用其形成的半导体器件

    公开(公告)号:US20070273029A1

    公开(公告)日:2007-11-29

    申请号:US11839478

    申请日:2007-08-15

    CPC classification number: G03F1/00 G03F1/70

    Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

    Abstract translation: 用于形成多层互连线的光掩模组和使用其形成的半导体器件包括用于形成下互连线的第一光掩模和用于形成上互连线的第二光掩模。 第一和第二光掩模具有彼此平行的较低的不透明图案和与下部不透明图案重叠的上部不透明图案。 在这种情况下,下部不透明图案的端部位于与下部不透明图案交叉的直线上。 结果,当使用第二光掩模形成上互连线时,即使反射光聚焦,也可以防止形成差的光刻胶图形。

    METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY
    13.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY 审中-公开
    使用选择性外延生长和部分平面化技术制造半导体集成电路的方法和半导体集成电路制造的方法

    公开(公告)号:US20070241335A1

    公开(公告)日:2007-10-18

    申请号:US11766655

    申请日:2007-06-21

    CPC classification number: H01L27/1108 H01L27/11

    Abstract: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

    Abstract translation: 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层,并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层,并且对半导体本体层进行图案化以形成半导体本体。 结果,半导体本体包括单晶外延半导体图案的至少一部分。 因此,半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

    MICROFLUIDIC DEVICE CAPABLE OF EQUALIZING FLOW OF MULTIPLE MICROFLUIDS IN CHAMBER, AND MICROFLUIDIC NETWORK EMPLOYING THE SAME
    15.
    发明申请
    MICROFLUIDIC DEVICE CAPABLE OF EQUALIZING FLOW OF MULTIPLE MICROFLUIDS IN CHAMBER, AND MICROFLUIDIC NETWORK EMPLOYING THE SAME 失效
    能够平衡室内多种微流体流动的微流体装置和使用其的微流控网络

    公开(公告)号:US20080072964A1

    公开(公告)日:2008-03-27

    申请号:US11675146

    申请日:2007-02-15

    Abstract: Provided are a microfluidic device and a microfluidic network formed by connecting such microfluidic devices. The microfluidic device can equalize the flow of multiple microfluids in a chamber in parallel to thereby have an equal flow rate when the microfluids transferred through different flow channels join in the chamber having a changing cross-sectional area. The microfluidic device includes: multiple flow channels formed between an upper substrate and a lower substrate to transfer the microfluids and including inlets for injecting the microfluids in one side and fluid stopping surfaces for stopping the flow of the microfluids in the other side; a pressure controlling flow channel for removing a pressure difference between the microfluids; a fluid converging part for converging the microfluids; and a chamber composed of hydrophilic surfaces and hydrophobic surfaces disposed alternately in a flow direction so that the microfluids join and flow in parallel and equal.

    Abstract translation: 提供了通过连接这种微流体装置形成的微流体装置和微流体网络。 微流体装置可以平行地均衡腔室中的多个微流体的流动,从而当通过不同流动通道传送的微流体连接在具有变化的横截面积的腔室中时具有相等的流速。 微流体装置包括:在上基板和下基板之间形成的多个流动通道,以转移微流体并且包括用于在一侧注入微流体的入口和用于阻止另一侧的微流体流动的流体停止表面; 用于去除所述微流体之间的压力差的压力控制流路; 用于会聚微流体的流体收敛部分; 以及由流动方向交替设置的亲水性表面和疏水性表面构成的室,使得微流体并流并平行流动。

    Apparatus and Method for Scheduling Multiuser/Single User in Multiple Input Multiple Output (MIMO) System
    17.
    发明申请
    Apparatus and Method for Scheduling Multiuser/Single User in Multiple Input Multiple Output (MIMO) System 有权
    在多输入多输出(MIMO)系统中调度多用户/单用户的装置和方法

    公开(公告)号:US20080025336A1

    公开(公告)日:2008-01-31

    申请号:US11782629

    申请日:2007-07-24

    Abstract: An apparatus and method for scheduling a multiuser and a single user in a Multiple Input Multiple Output (MIMO) system are provided. The method for scheduling a multiuser and a single user at BS in MIMO system includes determining ratios of MultiUser-MIMO (MU-MIMO) chunks and Single User-MIMO (SU-MIMO) chunks to allocation chunks, determining the MU-MIMO chunks in the determined ratio and the remaining chunks as the SU-MIMO chunks, transmitting chunk information relating to the determined chunks to one or more Mobile Stations (MSs), and, when Channel Quality Information (CQI) feedback information relating to the determined MU-MIMO chunks and the determined SU-MIMO chunks is received from the MSs, allocating chunks and streams for MU-MIMO/SU-MIMO to users who maximize overall capacity using the CQI feedback information.

    Abstract translation: 提供了一种用于在多输入多输出(MIMO)系统中调度多用户和单个用户的装置和方法。 在MIMO系统中在BS处调度多用户和单个用户的方法包括:将多用户MIMO(MU-MIMO)块和单用户MIMO(SU-MIMO)块的比率确定为分组块,确定MU-MIMO块中的MU-MIMO块 确定的比率和剩余的块作为SU-MIMO块,将与所确定的块相关的块信息发送到一个或多个移动站(MS),以及当与确定的MU-MIMO相关的信道质量信息(CQI)反馈信息 块,并且从MS接收确定的SU-MIMO块,将用于MU-MIMO / SU-MIMO的块和流分配给使用CQI反馈信息最大化总体容量的用户。

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