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    Gate driving circuit and display device having the same
    11.
    发明申请
    Gate driving circuit and display device having the same 有权
    栅极驱动电路及其显示装置

    公开(公告)号：US20090040203A1

    公开(公告)日：2009-02-12

    申请号：US12218814

    申请日：2008-07-18

    申请人： Sung-Man Kim ,  Hong-Woo Lee ,  Myung-Koo Hur ,  Hee-Joon Kim

    发明人： Sung-Man Kim ,  Hong-Woo Lee ,  Myung-Koo Hur ,  Hee-Joon Kim

    IPC分类号： G06F3/038

    CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184

    摘要： A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

    摘要翻译： 一种栅极驱动电路和具有该栅极驱动电路的显示装置，上拉单元在一帧的第一周期期间通过使用第一时钟信号来上拉电流门信号。 耦合到上拉单元的上拉驱动器从前一级之一接收进位信号，以接通上拉单元。 上拉单元接收来自下一级中的一个的门信号，将当前门信号放电至截止电压电平，并关闭上拉单元。 持有者将当前门信号保持在电压电平。 逆变器响应于第一个时钟信号打开/关闭支架。 波纹防止器具有与上拉单元的输出端子共同耦合的源极和栅极，以及耦合到反相器的输入端子的漏极，并且包括用于防止纹波施加到逆变器的纹波防止二极管 。

    Display apparatus
    12.
    发明授权
    Display apparatus 有权
    显示装置

    公开(公告)号：US08194057B2

    公开(公告)日：2012-06-05

    申请号：US11782967

    申请日：2007-07-25

    申请人： Hong-Woo Lee ,  Myung-Koo Hur ,  Jong-Hwan Lee

    发明人： Hong-Woo Lee ,  Myung-Koo Hur ,  Jong-Hwan Lee

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3659 ,  G09G3/2074 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0447

    摘要： A display apparatus has a pixel including a main pixel connected to a main gate line and a data line, and a sub-pixel connected to a sub-gate line and the data line. A main gate driver outputs a main gate pulse to the main gate line during a time period 1H. A sub-gate driver receives the main gate pulse and outputs a sub-gate pulse to the sub-gate line during a first portion of time period 1H. The data driver applies a sub-pixel voltage to the data line during the first portion of time period 1H and applies the main pixel voltage to the data line during a second portion of time period 1H.

    摘要翻译： 显示装置具有包括连接到主栅极线和数据线的主像素的像素，以及连接到子栅极线和数据线的子像素。 主栅极驱动器在时间段1H内向主栅极线输出主栅极脉冲。 子栅极驱动器在时间段1H的第一部分期间接收主栅极脉冲并将子栅极脉冲输出到子栅极线。 数据驱动器在时间段1H的第一部分期间向数据线施加子像素电压，并且在时间段1H的第二部分期间将主像素电压施加到数据线。

    Liquid crystal display having a defect repair mechanism interposed between a light shielding storage line and a light shielding output electrode
    13.
    发明授权
    Liquid crystal display having a defect repair mechanism interposed between a light shielding storage line and a light shielding output electrode 失效
    液晶显示器具有介于遮光存储线和遮光输出电极之间的缺陷修复机构

    公开(公告)号：US07612863B2

    公开(公告)日：2009-11-03

    申请号：US11744457

    申请日：2007-05-04

    申请人： Beom-Jun Kim ,  Jong-Hwan Lee ,  Sang-Jin Jeon ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

    发明人： Beom-Jun Kim ,  Jong-Hwan Lee ,  Sang-Jin Jeon ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

    IPC分类号： G02F1/13 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/136

    CPC分类号： G02F1/136213 ,  G02F1/136259 ,  G02F1/136286

    摘要： A liquid crystal display that is subject to pixel-high defects due to manufacturing anomalies is provided with programmable repair means for each pixel electrode. In one embodiment, a transistor-array substrate is provided with plural gate lines that are separated from each other by a first interval, plural data lines that are insulated from the gate lines while crossing the gate lines, and separated from each other by a second interval larger than the first interval, thereby defining plural pixel areas. Each pixel area has a corresponding pixel unit comprising a switching device, pixel electrode, and repair electrode. The repair electrode branches from a neighboring gate line and extends such that the repair electrode is in overlapping spaced-apart relation with the pixel electrode and selectively connectable to the pixel electrode. Accordingly, a pixel where a high pixel defect occurs can be repaired by selective connection with the repair electrode, thereby improving display quality of the liquid crystal display.

    摘要翻译： 由于制造异常而受到像素高缺陷的液晶显示器，为每个像素电极提供可编程修复装置。 在一个实施例中，晶体管阵列基板设置有多个栅极线，它们彼此分开第一间隔，多条数据线在与栅极线交叉时与栅极线绝缘并且彼此分开第二个 间隔大于第一间隔，从而限定多个像素区域。 每个像素区域具有包括开关器件，像素电极和修复电极的对应像素单元。 修复电极从相邻的栅极线分支并延伸，使得修复电极与像素电极重叠间隔开，并且可选择性地连接到像素电极。 因此，可以通过与修复电极的选择性连接来修复发生高像素缺陷的像素，从而提高液晶显示器的显示质量。

    GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME
    14.
    发明申请
    GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
    闸门驱动电路和显示装置

    公开(公告)号：US20090189679A1

    公开(公告)日：2009-07-30

    申请号：US12338182

    申请日：2008-12-18

    申请人： Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

    发明人： Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

    IPC分类号： H03K17/687 ,  G02F1/1368

    CPC分类号： G09G3/3677 ,  G11C19/184 ,  H03K17/165

    摘要： A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

    摘要翻译： 栅极驱动电路包括级联级，每级包括上拉部分，进位部分，上拉驱动部分，保持部分和逆变器。 上拉部分将输入时钟的栅极电压上拉。 进位部分将输入电压提升到输入时钟。 上拉驱动部分连接到与进位部分和上拉部分相同的控制端子（Q-节点），并且从前一级接收先前的进位电压以打开上拉部分和进位 部分。 保持部将栅极电压保持在截止电压，逆变器基于逆变器时钟来控制保持部的开启和关闭保持部中的至少一个。 给定水平周期（1H）中的高电平的反相器时钟在时间上在预定时间间隔的输入时钟的高电平之前。

    LIQUID CRYSTAL DISPLAY HAVING DEFECT REPAIR MECHANISM
    15.
    发明申请
    LIQUID CRYSTAL DISPLAY HAVING DEFECT REPAIR MECHANISM 失效
    具有缺陷修复机构的液晶显示

    公开(公告)号：US20070263134A1

    公开(公告)日：2007-11-15

    申请号：US11744457

    申请日：2007-05-04

    申请人： Beom-Jun Kim ,  Jong-Hwan Lee ,  Sang-Jin Jeon ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

    发明人： Beom-Jun Kim ,  Jong-Hwan Lee ,  Sang-Jin Jeon ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

    IPC分类号： G02F1/1333

    CPC分类号： G02F1/136213 ,  G02F1/136259 ,  G02F1/136286

    摘要： A liquid crystal display that is subject to pixel-high defects due to manufacturing anomalies is provided with programmable repair means for each pixel electrode. In one embodiment, a transistor-array substrate is provided with plural gate lines that are separated from each other by a first interval, plural data lines that are insulated from the gate lines while crossing the gate lines, and separated from each other by a second interval larger than the first interval, thereby defining plural pixel areas. Each pixel area has a corresponding pixel unit comprising a switching device, pixel electrode, and repair electrode. The repair electrode branches from a neighboring gate line and extends such that the repair electrode is in overlapping spaced-apart relation with the pixel electrode and selectively connectable to the pixel electrode. Accordingly, a pixel where a high pixel defect occurs can be repaired by selective connection with the repair electrode, thereby improving display quality of the liquid crystal display.

    摘要翻译： 由于制造异常而受到像素高缺陷的液晶显示器，为每个像素电极提供可编程修复装置。 在一个实施例中，晶体管阵列基板设置有多条栅极线，它们彼此分开第一间隔，多条数据线在与栅极线交叉的同时与栅极线绝缘并且彼此分开第二个 间隔大于第一间隔，从而限定多个像素区域。 每个像素区域具有包括开关器件，像素电极和修复电极的对应像素单元。 修复电极从相邻的栅极线分支并延伸，使得修复电极与像素电极重叠间隔开，并且可选择性地连接到像素电极。 因此，可以通过与修复电极的选择性连接来修复发生高像素缺陷的像素，从而提高液晶显示器的显示质量。

    Method of driving a gate line and gate drive circuit for performing the method
    16.
    发明授权
    Method of driving a gate line and gate drive circuit for performing the method 有权
    驱动用于执行该方法的栅极线和栅极驱动电路的方法

    公开(公告)号：US08565370B2

    公开(公告)日：2013-10-22

    申请号：US13612532

    申请日：2012-09-12

    申请人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

    发明人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

    摘要： A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

    摘要翻译： 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。

    Gate drive circuit and display apparatus having the same
    18.
    发明授权
    Gate drive circuit and display apparatus having the same 有权
    栅极驱动电路和具有该栅极驱动电路的显示装置

    公开(公告)号：US08619070B2

    公开(公告)日：2013-12-31

    申请号：US12970787

    申请日：2010-12-16

    申请人： Hong-Woo Lee ,  Eung-Gyu Lee ,  Jong-Hwan Lee ,  Sung-Man Kim

    发明人： Hong-Woo Lee ,  Eung-Gyu Lee ,  Jong-Hwan Lee ,  Sung-Man Kim

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2340/0492

    摘要： An n-th stage (wherein, n is an integer) of the stages of a gate driving circuit includes a pull-up part, a first variable mode part and a second variable mode part. At least one of the first and second variable mode parts includes a variable element. The variable element comprises a first thin-film transistor (TFT) turned on in response to a first level voltage of the first or second direction signal, a second TFT applying the first or second direction signal to a control part of the pull-up part in response to an output signal of a previous stage or an output signal of a next stage, and a third TFT connected to the second TFT through the first TFT.

    摘要翻译： 栅极驱动电路的级的第n级（其中，n是整数）包括上拉部分，第一可变模式部分和第二可变模式部分。 第一和第二可变模式部件中的至少一个包括可变元件。 可变元件包括响应于第一或第二方向信号的第一电平电压而导通的第一薄膜晶体管（TFT），将第一或第二方向信号施加到上拉部分的控制部分的第二TFT 响应于前一级的输出信号或下一级的输出信号，以及通过第一TFT连接到第二TFT的第三TFT。

    Method of driving a gate line and gate drive circuit for performing the method
    19.
    发明授权
    Method of driving a gate line and gate drive circuit for performing the method 有权
    驱动用于执行该方法的栅极线和栅极驱动电路的方法

    公开(公告)号：US08306177B2

    公开(公告)日：2012-11-06

    申请号：US12575895

    申请日：2009-10-08

    申请人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

    发明人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

    摘要： A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

    摘要翻译： 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。

    Gate driving circuit and display apparatus having the same
    20.
    发明授权
    Gate driving circuit and display apparatus having the same 有权
    栅极驱动电路及其显示装置

    公开(公告)号：US08098227B2

    公开(公告)日：2012-01-17

    申请号：US12338182

    申请日：2008-12-18

    申请人： Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

    发明人： Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3677 ,  G11C19/184 ,  H03K17/165

    摘要： A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

    摘要翻译： 栅极驱动电路包括级联级，每级包括上拉部分，进位部分，上拉驱动部分，保持部分和逆变器。 上拉部分将输入时钟的栅极电压上拉。 进位部分将输入电压提升到输入时钟。 上拉驱动部分连接到与进位部分和上拉部分相同的控制端子（Q-节点），并且从前一级接收先前的进位电压以打开上拉部分和进位 部分。 保持部将栅极电压保持在截止电压，逆变器基于逆变器时钟来控制保持部的开启和关闭保持部中的至少一个。 给定水平周期（1H）中的高电平的反相器时钟在时间上在预定时间间隔的输入时钟的高电平之前。