公开(公告)号：US09606454B2

公开(公告)日：2017-03-28

申请号：US14022657

申请日：2013-09-10

申请人： Takashi Taguchi ,  Joji Kuwahara

发明人： Takashi Taguchi ,  Joji Kuwahara

IPC分类号： G03B27/42 ,  G03F7/20

CPC分类号： G03F7/70691 ,  G03F7/70733

摘要： A substrate processing apparatus includes a processing section and an exposure transport section. The exposure transport section includes a horizontal transport region and a plurality of vertical transport regions in a casing. The horizontal transport region is provided at the upper portion of the casing to extend in the X direction. A plurality of exposure devices are arranged below the horizontal transport region to be lined up in the X direction. A transport mechanism is provided in the horizontal transport region. The transport mechanism is configured to be capable of transporting a substrate between the processing section and the plurality of exposure devices.

公开(公告)号：US09170459B2

公开(公告)日：2015-10-27

申请号：US13858958

申请日：2013-04-09

申请人： Takashi Taguchi

发明人： Takashi Taguchi

IPC分类号： G02F1/1339 ,  G02F1/1341 ,  H01J9/26 ,  H01J9/32

CPC分类号： G02F1/1339 ,  G02F1/1341 ,  G02F2001/13415

摘要： A liquid crystal display device includes: a pair of substrates disposed to face each other with a predetermined distance therebetween; a seal pattern, provided between the pair of substrates and has a closed-loop shape to surround and seal a liquid crystal, wherein the liquid crystal is provided in a form of a plurality of droplets on one of the pair of substrates and then is sandwiched between the pair of substrates, so that the plurality of droplets are respectively spread and sealed in a region surrounded by the seal pattern; and a dummy pattern, which is formed on the one substrate in the region surrounded by the seal pattern and has a height less than half of the predetermined distance, the dummy pattern being arranged adjacent to and in parallel to the seal pattern and in a range to which one droplet is spread out.

摘要翻译： 液晶显示装置包括：一对基板，以彼此间隔预定距离彼此面对; 密封图案，设置在所述一对基板之间并且具有围绕和密封液晶的闭环形状，其中所述液晶以所述一对基板中的一个基板上的多个液滴的形式设置，然后被夹在 在所述一对基板之间，使得所述多个液滴分别展开并密封在由所述密封图案包围的区域中; 以及虚设图案，其形成在由密封图案包围的区域中的一个基板上，并且具有小于预定距离的一半的高度，该虚设图案被布置为与密封图案相邻并平行，并且在一定范围内 将一个液滴展开。

公开(公告)号：US20070200816A1

公开(公告)日：2007-08-30

申请号：US11679532

申请日：2007-02-27

申请人： Takashi Taguchi

发明人： Takashi Taguchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0289

摘要： A semiconductor integrated circuit device includes first to k-th decoders, and a MOS transistor switch group having a hierarchical structure of first to k-th hierarchies and operated on a second voltage level. An n-bit input signal of a first voltage level is divided into k groups (k is an integral number equal to or larger than 2) and input to the first to k-th decoders. The first to k-th decoders decode the input signal, shift the decode results to the second voltage level higher than the first voltage level and output the same. The MOS transistor switch group is supplied with 2n analog inputs at the first hierarchy, selects one of the 2n analog inputs and outputs the selected analog input from the k-th hierarchy.

摘要翻译： 半导体集成电路器件包括第一至第k解码器和具有第一至第k层级的分层结构并在第二电压电平上操作的MOS晶体管开关组。 第一电压电平的n位输入信号被分成k组（k是等于或大于2的整数），并输入到第一至第k解码器。 第一至第k解码器对输入信号进行解码，将解码结果转换到高于第一电压电平的第二电压电平并输出。 MOS晶体管开关组在第一层提供2个模拟输入，选择2个模拟输入端之一，并输出第k个 层次结构。

公开(公告)号：US20060079017A1

公开(公告)日：2006-04-13

申请号：US11163278

申请日：2005-10-12

申请人： Takashi Taguchi

发明人： Takashi Taguchi

IPC分类号： H01L21/302 ,  H01L21/00 ,  H01L21/461

CPC分类号： H01Q19/062 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02327 ,  H01Q15/08

摘要： A method for manufacturing a microlens formed on a semiconductor substrate includes the steps of preparing the semiconductor substrate, forming an insulating film, which has high etching selectivity with the semiconductor substrate, on the semiconductor substrate, forming a first resist layer, which has an opening that exposes a part of the insulating film, on the insulating film, forming a lens forming portion by eliminating a part of the insulting film, using the first resist layer as a mask, forming a second resist layer, which has roughly cylindrical shape, on the lens forming portion surrounded by the insulating film, transforming the second resist layer into a third resist layer that has roughly hemispheric shape by reflowing the second resist later with a heat treatment, and forming a lens on the semiconductor substrate by etching the third resist layer, the semiconductor substrate, and the insulating film simultaneously with anisotropic etching.

摘要翻译： 一种制造在半导体衬底上形成的微透镜的方法包括以下步骤：在半导体衬底上制备半导体衬底，形成与半导体衬底具有高蚀刻选择性的绝缘膜，形成第一抗蚀剂层，该第一抗蚀剂层具有开口 通过使用第一抗蚀剂层作为掩模，通过去除绝缘膜的一部分而在绝缘膜上暴露出绝缘膜的一部分，形成透镜形成部分，形成具有大致圆筒形的第二抗蚀剂层 所述透镜形成部分被所述绝缘膜包围，然后通过热处理将所述第二抗蚀剂层转换成具有大致半球形状的第三抗蚀剂层，并且通过蚀刻所述第三抗蚀剂层在所述半导体衬底上形成透镜 ，半导体衬底和绝缘膜同时进行各向异性蚀刻。

公开(公告)号：US20050186756A1

公开(公告)日：2005-08-25

申请号：US11048891

申请日：2005-02-03

申请人： Sachiko Yabe ,  Takashi Taguchi ,  Minoru Watanabe

发明人： Sachiko Yabe ,  Takashi Taguchi ,  Minoru Watanabe

IPC分类号： H01L21/762 ,  H01L21/027 ,  H01L21/76 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film has both openings to permit local oxidization in the integrated circuit area, and an opening defining an alignment mark adjacent to the circuit area. The alignment mark may be formed either in the semiconductor and insulator layers, or in a part of the nitride film left after the nitride film is removed from the circuit area. In either case, the edge height of the alignment mark is not limited by the thickness of the semiconductor layer. Using the nitride layer to define both the alignment mark and the field oxide reduces the necessary number of fabrication steps.

摘要翻译： 在具有半导体层和下层绝缘体层的衬底中制造半导体集成电路。 制造工艺包括将半导体层局部氧化以形成场氧化物的步骤，在该步骤期间半导体层被氮化物膜保护。 氮化物膜具有两个开口以允许集成电路区域中的局部氧化，以及限定与电路区域相邻的对准标记的开口。 对准标记可以形成在半导体层和绝缘体层中，或者在从电路区域去除氮化物膜之后残留的氮化膜的一部分中。 在任一情况下，对准标记的边缘高度不受半导体层的厚度的限制。 使用氮化物层来限定对准标记和场氧化物两者减少了必要数量的制造步骤。

公开(公告)号：US20050161159A1

公开(公告)日：2005-07-28

申请号：US11008842

申请日：2004-12-10

申请人： Yoshihisa Yamada ,  Masafumi Maeda ,  Takashi Taguchi

发明人： Yoshihisa Yamada ,  Masafumi Maeda ,  Takashi Taguchi

IPC分类号： B65G49/07 ,  H01L21/00 ,  H01L21/027 ,  H01L21/677 ,  H01L21/306

CPC分类号： H01L21/67748 ,  H01L21/67178 ,  H01L21/67225 ,  H01L21/67276 ,  Y10S414/135

摘要： A forward direction-only path (first substrate transport path) is formed for transporting substrates in a forward direction to pass the substrates on to an exposing apparatus. A separate, substrate transport path (second substrate transport path) is formed exclusively for post-exposure bake (PEB). Substrate transport along each path is carried out independently of substrate transport along the other. A fourth main transport mechanism is interposed as a predetermined substrate transport mechanism between transfer points consisting of a buffer acting as a temporary storage module for temporarily storing the substrates and a post-exposure bake (PEB) unit corresponding to a predetermined treating unit. This arrangement forms the path for transporting the substrates between the buffer and the PEB unit, to allow PEB treatment of the substrates to be performed smoothly. Similarly, the substrates are transported smoothly to the buffer.

摘要翻译： 形成向前方向路径（第一基板输送路径），用于沿正向方向输送基板，使基板通过曝光装置。 单独的基板输送路径（第二基板输送路径）专门用于后曝光烘烤（PEB）。 沿着每个路径的基板传送独立于沿着另一个的基板传送进行。 第四主要传送机构作为预定的基板传送机构，在由用作临时存储基板的临时存储模块的缓冲器和对应于预定处理单元的曝光后烘烤（PEB）单元组成的传送点之间。 该布置形成用于在缓冲器和PEB单元之间传送基板的路径，以允许平滑地执行基板的PEB处理。 类似地，衬底被平滑地输送到缓冲器。

公开(公告)号：US06191779B1

公开(公告)日：2001-02-20

申请号：US09114195

申请日：1998-07-13

申请人： Takashi Taguchi ,  Tetsuro Itakura

发明人： Takashi Taguchi ,  Tetsuro Itakura

IPC分类号： G09G500

CPC分类号： G09G3/2011 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2330/023

摘要： A liquid crystal display device significantly reduces power consumption and causes no signal delay when a liquid crystal panel performs an inversion-type drive. The liquid crystal display device comprises a digital controller, a level shift circuit, a digital-to-analog (D/A) converter, a liquid crystal panel, and a plurality of capacitors. In the D/A converter, a charging control circuit is provided corresponding to each capacitor. The charging control circuit comprises a switch, a diode and an inverter, the switch and the diode being coupled in parallel. The switch is turned on and off in response to a switching signal from the digital controller. The switch is changed to a turning- on state during a blanking period after one horizontal displaying. Upon turning-on of the switch, the capacitors are charged. Digital pixel data outputted from the digital controller undergoes a level changing depending on a voltage across the electrodes of the capacitors, according to a charge conservation.

摘要翻译： 液晶显示装置显着地降低功耗，并且当液晶面板进行反转型驱动时不产生信号延迟。 液晶显示装置包括数字控制器，电平移位电路，数模（D / A）转换器，液晶面板和多个电容器。 在D / A转换器中，对应于每个电容器提供充电控制电路。 充电控制电路包括开关，二极管和反相器，开关和二极管并联耦合。 响应于来自数字控制器的切换信号，开关被打开和关闭。 在一个水平显示之后，在消隐期间，开关变为开启状态。 在开关接通时，电容器被充电。 根据电荷保持，从数字控制器输出的数字像素数据根据电容器的电极两端的电压进行电平变化。

公开(公告)号：US5342713A

公开(公告)日：1994-08-30

申请号：US949824

申请日：1992-12-18

申请人： Hiroshi Ohtsuka ,  Kazutoshi Abe ,  Takashi Taguchi

发明人： Hiroshi Ohtsuka ,  Kazutoshi Abe ,  Takashi Taguchi

IPC分类号： G03F1/00 ,  G03F9/00

CPC分类号： G03F1/30

摘要： The present invention relates to a phase shifting mask for use in a photolithographic process of forming a wiring pattern. The phase shifting mask comprises a transparent base plate (11), shading layers (12) formed selectively on the transparent base plate (11), and two kinds of phase shifting layers (13a, 13b) formed on transparent portions of the transparent base plate between the adjacent shading layers, respectively. The phase difference of the two kinds of phase shifting layers (13a, 13b) relative to the transparent base plate (11) is 90.degree., and the phase difference between the phase shifting layers is 180.degree.. The transfer of an unnecessary pattern in the shifter edge portion can be obviated by using the shading layers having a phase difference of 90.degree. relative to the transparent base plate.

摘要翻译： PCT No.PCT / JP91 / 00817 Sec。 371日期1992年12月18日 102（e）日期1992年12月18日PCT Filed 1991年6月19日PCT Pub。 WO91 / 20018 PCT出版物 日期1991年12月26日。本发明涉及用于形成布线图案的光刻工艺中的相移掩模。 相移掩模包括透明基板（11），选择性地形成在透明基板（11）上的遮光层（12）和形成在透明基板的透明部分上的两种相移层（13a，13b） 在相邻的遮光层之间。 两种相移层（13a，13b）相对于透明基板（11）的相位差为90°，相移层之间的相位差为180°。 可以通过使用相对于透明基板的相位差为90°的遮光层来消除移位器边缘部分中不需要的图案的转印。

公开(公告)号：US08631809B2

公开(公告)日：2014-01-21

申请号：US12725981

申请日：2010-03-17

申请人： Tetsuya Hamada ,  Takashi Taguchi

发明人： Tetsuya Hamada ,  Takashi Taguchi

IPC分类号： B08B3/00

CPC分类号： G03F7/20 ,  H01L21/67178 ,  H01L21/67225 ,  H01L21/67303 ,  H01L21/67742 ,  H01L21/67748 ,  Y10S134/902

摘要： An interface block is constituted by a cleaning/drying processing block and a carry-in/carry-out block. The cleaning/drying processing block includes cleaning/drying processing sections and a transport section. The transport section is provided with a transport mechanism. The carry-in/carry-out block is provided with a transport mechanism. The transport mechanism carries substrates in and out of an exposure device.

摘要翻译： 接口块由清洁/干燥处理块和进/出块组成。 清洁/干燥处理块包括清洁/干燥处理部分和传送部分。 运输部分设有运输机构。 输入/输出块具有传送机构。 输送机构将基板输入和移出曝光装置。

公开(公告)号：US08502560B2

公开(公告)日：2013-08-06

申请号：US13235953

申请日：2011-09-19

申请人： Takashi Taguchi ,  Hiroyuki Ideno

发明人： Takashi Taguchi ,  Hiroyuki Ideno

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K3/35613 ,  H03K19/09429

摘要： An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

摘要翻译： 输出电路，其根据来自输出端子的输入信号输出输出信号，并根据阻抗控制信号使输出端子成为高阻抗状态。 输出电路包括在其源极处连接到第一电源的输出pMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和地之间的输出nMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和输出nMOS晶体管的漏极之间的输出端子。 输出电路包括第一电平移位器电路，其输出来自第一栅极控制端子的第一栅极控制信号以控制输出pMOS晶体管的导通/截止。 输出电路包括第二电平移位器电路，其输出来自第二栅极控制端子的第二栅极控制信号以控制输出nMOS晶体管的导通/截止。