公开(公告)号：US06620725B1

公开(公告)日：2003-09-16

申请号：US09395287

申请日：1999-09-13

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

摘要翻译： 描述用于在两个步骤中执行CMP的过程。 在沟槽已经形成并且用铜过度填充之后，在本发明的第一实施例中，最初使用硬焊盘去除大部分铜，直到达到一个点，其中凹陷效应将开始出现。 然后取代软焊盘，继续CMP直到除了沟槽中除去所有的铜。 在第二实施例中，使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。 如前所述，使用这种组合，直到达到点，其中凹陷效应将开始出现。 然后，除了沟槽之外，使用相对较低的压力结合相对高的转速直到除去所有的铜。 这两个实施例都导致刚好填充铜的沟槽，几乎没有凹陷效应，并且除了沟槽本身之外，所有痕迹的铜都被去除。

公开(公告)号：US06417106B1

公开(公告)日：2002-07-09

申请号：US09431150

申请日：1999-11-01

申请人： Jih-Churng Twu ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

发明人： Jih-Churng Twu ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01L21302

CPC分类号： H01L21/7684 ,  H01L21/76829

摘要： A process for reducing dishing in damascene structures formed in low k organic dielectrics is described. A key feature is the insertion of a liner layer between the low k dielectric layer and the etch stop layer. The only requirement for the liner material is that it should have different etching characteristics from the etch stop material so that when trenches are etched in the dielectric they extend as far as the etch stop layer, in the normal way. When this is done it is found that dishing, after CMP, is significantly reduced, particularly for trench structures made up of multiple narrow trenches spaced close together.

摘要翻译： 描述了一种用于减少在低k有机电介质中形成的镶嵌结构中的凹陷的方法。 一个关键特征是在低k电介质层和蚀刻停止层之间插入衬里层。 衬垫材料的唯一要求是它应该具有与蚀刻停止材料不同的蚀刻特性，使得当在电介质中蚀刻沟槽时，它们以正常方式延伸到蚀刻停止层的最远处。 当这样做时，发现在CMP之后的凹陷显着减少，特别是对于由几个间隔得很近的窄沟槽组成的沟槽结构。

公开(公告)号：US06706577B1

公开(公告)日：2004-03-16

申请号：US09298879

申请日：1999-04-26

申请人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L218238

CPC分类号： H01L21/823857 ,  H01L27/10894

摘要： A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.

摘要翻译： 描述了使用两步湿氧化工艺同时形成用于高压和低压晶体管的差分栅极氧化物的方法。 提供一种半导体衬底，其中衬底的有源区域与其他有源区域隔离，并且其中存在将形成低压晶体管的至少一个低电压区域和至少一个高电压区域，其中高压晶体管将 形成。 半导体衬底的表面被湿式氧化以在有源区域中在半导体衬底的表面上形成第一层栅极氧化物层。 低电压有源区域用掩模覆盖。 半导体衬底的表面被再次湿式氧化，其中未被掩模覆盖，以在高电压有源区的第一栅氧化层下形成第二层栅氧化层。 去除面具。 一层多晶硅被沉积在低电压有源区中的第一栅极氧化物层上并覆盖在高电压有源区中的第二栅极氧化物层上并被图案化以在制造中形成低电压和高压晶体管的栅电极 集成电路。

公开(公告)号：US06753249B1

公开(公告)日：2004-06-22

申请号：US09759908

申请日：2001-01-16

申请人： Ying-Ho Chen ,  Jih-Churng Twu ,  Weng Chang

发明人： Ying-Ho Chen ,  Jih-Churng Twu ,  Weng Chang

IPC分类号： H01L214763

CPC分类号： H01L21/7684

摘要： An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.

摘要翻译： 公开了一种改进的新工艺，用于消除铜线损伤，铜缺陷，不均匀性改进，具有较低的凹陷和侵蚀。 本发明涉及一种用于半导体集成电路器件的制造方法，更具体地说，涉及通过在低温下沉积由机械硬膜和软膜组成的多层界面材料来消除镶嵌加工中的铜线损伤 介电常数，层间金属电介质（IMD）和随后的化学机械抛光（CMP）回退多余的材料以使表面平坦化。

公开(公告)号：US06391780B1

公开(公告)日：2002-05-21

申请号：US09378949

申请日：1999-08-23

申请人： Tsu Shih ,  Ying-Ho Chen ,  Jih-Churng Twu

发明人： Tsu Shih ,  Ying-Ho Chen ,  Jih-Churng Twu

IPC分类号： H01L21302

CPC分类号： H01L21/3212

摘要： A process for manufacturing damascene wiring in integrated circuits is described. Trenches in the top most layer are first over-filled with a soft metal (such as copper) and then a relatively thin layer of a hard material such as tantalum, tantalum nitride, titanium, titanium nitride etc is deposited on the copper surface Under a first set of control conditions CMP is then applied for just long enough to selectively remove this hard material layer from peaks in the copper surface while leaving it intact in the valleys. The control conditions for CMP are then adjusted so that CMP can proceed with material at the peaks being removed at a significantly faster rate than in the valleys. Thus, when the point is reached that all copper outside the trenches has been removed, the trenches are found to be just filled with a flat layer that has no dishing.

摘要翻译： 描述了在集成电路中制造镶嵌线的工艺。 首先用软金属（例如铜）填充最顶层的沟槽，然后在铜表面上沉积相对薄的硬质材料如钽，氮化钽，钛，氮化钛等层 第一组控制条件CMP然后施加足够长的时间以从铜表面的峰中选择性地去除该硬质材料层，同时将其完整地留在谷中。 然后调整CMP的控制条件，使得CMP可以以比在谷中明显更快的速率除去峰值处的材料继续进行。 因此，当达到沟槽外部的所有铜已经被去除的地方时，发现沟槽刚好填充有没有凹陷的平坦层。

公开(公告)号：US06227947B1

公开(公告)日：2001-05-08

申请号：US09366231

申请日：1999-08-03

申请人： Tien-Chen Hu ,  Jih-Churng Twu ,  Ying-Ho Chen ,  Tsu Shih

发明人： Tien-Chen Hu ,  Jih-Churng Twu ,  Ying-Ho Chen ,  Tsu Shih

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B53/013

摘要： An apparatus and a method for chemical mechanical polishing a metal on a semiconductor wafer capable of achieving improved pad life are disclosed. In the apparatus, in addition to a first spray nozzle used for spraying a slurry solution onto the top of a polishing pad, a second spray nozzle is provided for mounting juxtaposed to a conditioning pad for dispensing a cleaning solution capable of dissolving polishing debris formed on the polishing pad surface. The apparatus may further include at least one cleaning solution reservoir for storing and delivering a cleaning solution to the second spray nozzle. The method can be advantageously carried out in two-steps during which a first cleaning solution is sprayed onto the pad surface for dissolving the polishing debris, and then a second cleaning solution is sprayed onto the pad surface for removing or flushing away the dissolved debris. In one illustration for the removal of oxides of copper, an acid-containing or ammonium hydroxide-containing cleaning solution is used advantageously to dissolve the oxides, and then deionized water is used to remove the dissolved debris from the pad surface.

摘要翻译： 公开了一种用于化学机械抛光半导体晶片上的能够实现改善的焊盘寿命的装置和方法。 在该装置中，除了用于将浆液溶液喷洒到抛光垫的顶部上的第一喷嘴之外，还提供了第二喷嘴，用于与调节垫并置安装，用于分配能够溶解在 抛光垫表面。 该设备还可以包括至少一个清洁溶液储存器，用于将清洁溶液存储并输送到第二喷嘴。 该方法可以有利地在两个步骤中进行，在此期间将第一清洁溶液喷涂到垫表面上用于溶解抛光碎片，然后将第二清洁溶液喷涂到垫表面上以除去或冲洗掉溶解的碎屑。 在一个说明中，为了去除铜的氧化物，含有酸或氢氧化铵的清洗溶液有利地用于溶解氧化物，然后使用去离子水从衬垫表面去除溶解的碎屑。

公开(公告)号：US06162716A

公开(公告)日：2000-12-19

申请号：US277561

申请日：1999-03-26

申请人： Chen-Hua Yu ,  Jih-Churng Twu

发明人： Chen-Hua Yu ,  Jih-Churng Twu

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/3205

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/28061 ,  Y10S438/935

摘要： A method of forming an amorphous-Si (.alpha.-Si) gate with two or more .alpha.-Si layers with mismatched grains. The first embodiment involves forming two or more amorphous silicon layers over the gate dielectric. The amorphous silicon layers are formed insitu (in a reactor chamber without removing the wafer from the chamber). An amorphous silicon layer is deposited by exposing the substrate to a Silicon containing gas (E.g., SiH.sub.4). The Si containing gas flow is stopped. The chamber is pumped down and back filled with an inert gas to remove said silicon containing gas. In the next insitu step, the Si containing gas is restarted thus depositing the next amorphous Si layer. This deposition and purge cycle is repeated the desired number of times to form two or more mismatched .alpha.-Si layers. In the second embodiment, after an .alpha.-Si layer is deposited, the wafer is etched, for example in an HF vapor or wet clean. Then the wafer is returned to the chamber and another .alpha.-Si layer is formed thereover. The multi-layered .alpha.-Si gate is patterned and conventional processing completes the FET device. The .alpha.-Si gate prevents ion channeling to the gate dielectric.

摘要翻译： 用具有错配晶粒的两个或更多个α-Si层形成非晶Si（α-Si）栅极的方法。 第一实施例涉及在栅极电介质上形成两个或多个非晶硅层。 形成非晶硅层（在反应器室中，而不从室除去晶片）。 通过将衬底暴露于含硅气体（例如SiH 4）来沉积非晶硅层。 含Si的气流停止。 将该腔室向下泵送并填充惰性气体以除去所述含硅气体。 在下一个步骤中，重新开始含Si气体，从而沉积下一个非晶Si层。 将该沉积和清洗循环重复所需次数以形成两个或更多个不匹配的α-Si层。 在第二实施例中，在沉积α-Si层之后，蚀刻晶片，例如在HF蒸汽或湿清洁中。 然后将晶片返回到腔室，并在其上形成另一个α-Si层。 多层α-Si栅极被图案化，并且常规处理完成了FET器件。 α-Si栅极防止离子通道进入栅极电介质。

公开(公告)号：US06777251B2

公开(公告)日：2004-08-17

申请号：US10175702

申请日：2002-06-20

申请人： Ching Shan Lu ,  Fu-Su Lee ,  Wei-Ming You ,  Jih-Churng Twu ,  Yu-Chien Hsiao

发明人： Ching Shan Lu ,  Fu-Su Lee ,  Wei-Ming You ,  Jih-Churng Twu ,  Yu-Chien Hsiao

IPC分类号： H01L2166

CPC分类号： H01L21/67253 ,  H01L21/67098 ,  H01L22/20

摘要： A method including operating an ion implanted to implanting ions in a semiconductor wafer at a first ion dose level; performing a first thermal wave measurement to obtain the first thermal wave value; placing the semiconductor wafer in a rapid thermal annealing furnace and operating the furnace to rapidly heat the semiconductor wafer at a first rate for a first time period and so that the wafer is heated with intent of achieving a wafer temperature of 500° C.; performing a second thermal wave measurement to obtain a second thermal wave value; comparing the difference between the first thermal wave value and the second thermal wave value to a target range of 376.5-382.5 and rejecting the wafer as being outside of an acceptable specification if the difference is outside of the target range.

摘要翻译： 一种方法，包括操作注入的离子以在第一离子剂量水平下在半导体晶片中注入离子; 执行第一热波测量以获得第一热波值; 将半导体晶片放置在快速热退火炉中并操作炉子以第一速率第一时间段快速加热半导体晶片，并且旨在实现晶片温度为500℃的晶片被加热; 执行第二热波测量以获得第二热波值; 将第一热波值和第二热波值之间的差值与376.5-382.5的目标范围进行比较，并且如果差异在目标范围之外，则拒绝晶片超出可接受规范。

公开(公告)号：US06722949B2

公开(公告)日：2004-04-20

申请号：US09813238

申请日：2001-03-20

申请人： Tien-Chen Hu ,  Jih-Churng Twu

发明人： Tien-Chen Hu ,  Jih-Churng Twu

IPC分类号： B24B100

CPC分类号： B24B37/16 ,  B24B37/26 ,  B24D7/10

摘要： A ventilated platen/polishing pad assembly for chemical mechanical polishing copper conductors on a semiconductor wafer is disclosed. The ventilated platen is constructed by a platen having a multiplicity of apertures through a thickness of the platen, and a polishing pad that has a multiplicity of apertures for fluid communication with the multiplicity of apertures in the platen such that a gas can flow through the ventilated platen and the ventilated polishing pad to mix with a polishing slurry solution dispensed on top of the polishing pad. When an oxidizing gas is mixed with the slurry solution, the mass transfer process during the chemical mechanical polishing can be improved and thus improving the polishing uniformity of the copper surface. The invention further discloses a method for chemical mechanical polishing copper conductors on a semiconductor wafer by dispensing a polishing slurry/oxidizing gas mixture onto a top surface of a polishing pad for engaging a wafer surface and thus improving the polishing uniformity and preventing corrosion or erosion of the fresh copper surface by the acidic or basic components contained in the slurry solution.

摘要翻译： 公开了一种在半导体晶片上用于化学机械抛光铜导体的通风压板/抛光垫组件。 通风压板由具有穿过压板的厚度的多个孔的压板构成，抛光垫具有多个孔，用于与压板中的多个孔流体连通，使得气体可以流过通风的 压板和通风的抛光垫与分配在抛光垫顶部的抛光浆液混合。 当将氧化性气体与浆料溶液混合时，可以提高化学机械研磨过程中的传质过程，从而提高铜表面的研磨均匀性。 本发明还公开了一种通过将抛光浆料/氧化气体混合物分配到抛光垫的顶表面上用于接合晶片表面从而提高抛光均匀性并防止腐蚀或腐蚀的方法，用于化学机械抛光半导体晶片上的铜导体 新鲜的铜表面由浆液中所含的酸性或碱性成分溶液组成。

公开(公告)号：US06647998B2

公开(公告)日：2003-11-18

申请号：US09885772

申请日：2001-06-20

申请人： Jih-Churng Twu ,  Ming-Dar Guo ,  Tsung-Chieh Tsai ,  Sheng-Hsiung Tseng ,  Wei-Ming You ,  Yao-Pin Huang ,  Chia-Chun Cheng ,  Chin-Hsiung Ho ,  Ming Te More

发明人： Jih-Churng Twu ,  Ming-Dar Guo ,  Tsung-Chieh Tsai ,  Sheng-Hsiung Tseng ,  Wei-Ming You ,  Yao-Pin Huang ,  Chia-Chun Cheng ,  Chin-Hsiung Ho ,  Ming Te More

IPC分类号： B08B310

CPC分类号： H01L21/67034 ,  Y10S134/902

摘要： An electrostatic charge-free solvent-type dryer for drying semiconductor wafers after a wet bench process is disclosed in a preferred embodiment and in an alternate embodiment. In the preferred embodiment, the electrostatic charge-free solvent-type dryer is constructed by a tank body, a wafer carrier, an elevator means, a tank cover and a conduit for feeding the flow of solvent vapor. At least one of the tank cover, the conduit for feeding the flow of solvent vapor and the plurality of partition plates is fabricated of a non-electrostatic material such that electrostatic charge is not generated in the flow of solvent vapor. In the alternate embodiment, a deionizer is further provided in the tank cavity for producing a flux of positive ions to neutralize any negative ions that are possibly produced in the flow of solvent vapor.