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公开(公告)号：US20240222364A1
公开(公告)日：2024-07-04
申请号：US18188937
申请日：2023-03-23
Inventor： Tao-Yi HUNG , Jam-Wem LEE , Kuo-Ji CHEN , Wun-Jie LIN
IPC: H01L27/02 , H01L21/8234 , H01L23/528
CPC classification number: H01L27/0266 , H01L21/823475 , H01L23/5286
Abstract: An integrated circuit (IC) device includes an antenna effect protection device, and a to-be-protected device. A first source/drain of the antenna effect protection device is electrically coupled to a first conductor configured to carry a reference voltage. A second source/drain of the antenna effect protection device is electrically coupled by a second conductor to a gate of the to-be-protected device. The antenna effect protection device is a bulk-less device.
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公开(公告)号：US20240047453A1
公开(公告)日：2024-02-08
申请号：US18489652
申请日：2023-10-18
Inventor： Li-Wei CHU , Wun-Jie LIN , Yu-Ti SU , Ming-Fu TSAI , Jam-Wem LEE
CPC classification number: H01L27/0248 , H01L29/0649
Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.
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公开(公告)号：US20230064525A1
公开(公告)日：2023-03-02
申请号：US17459703
申请日：2021-08-27
Inventor： Chia-Wei HSU , Bo-Ting CHEN , Jam-Wem LEE
IPC: H01L29/06 , H01L23/528 , H01L27/02 , H01L23/522 , G06F30/3953 , G06F30/392 , G06F30/398
Abstract: A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.
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14.发明申请THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH INTER-LAYER VIAS AND INTRA-LAYER COUPLED TRANSISTORS 有权具有层间VIAS和层间耦合晶体管的三维集成电路公开(公告)号：US20150171062A1
公开(公告)日：2015-06-18
申请号：US14108454
申请日：2013-12-17
Inventor： Jam-Wem LEE
CPC classification number: H01L27/0207 , H01L25/11 , H01L25/50 , H01L27/0251 , H01L27/0255 , H01L27/0292 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L2924/0002 , H01L2924/00
Abstract: A circuit comprises a first layer and a second layer separate from the first layer. The first layer comprises a power line, a first transistor coupled to the power line, a second transistor coupled to the power line, and a first line coupling the first transistor and the second transistor. The second layer comprises a ground line, a third transistor coupled to the ground line, a fourth transistor coupled to the ground line, and a second line coupling the third transistor and the fourth transistor. The circuit also comprises an inter-layer interconnect that couples the first transistor and the third transistor. The inter-layer interconnect also couples the second transistor and the fourth transistor.
Abstract translation: 电路包括与第一层分开的第一层和第二层。 第一层包括电源线，耦合到电力线的第一晶体管，耦合到电力线的第二晶体管和耦合第一晶体管和第二晶体管的第一线。 第二层包括接地线，耦合到接地线的第三晶体管，耦合到接地线的第四晶体管，以及耦合第三晶体管和第四晶体管的第二线。 电路还包括耦合第一晶体管和第三晶体管的层间互连。 层间互连还耦合第二晶体管和第四晶体管。
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公开(公告)号：US20240106223A1
公开(公告)日：2024-03-28
申请号：US18518725
申请日：2023-11-24
Inventor： Yu-Hung YEH , Wun-Jie LIN , Jam-Wem LEE
CPC classification number: H02H3/08 , H02H1/0007
Abstract: An electrostatic discharge (ESD) protection circuit includes a first and second diode in a semiconductor wafer, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer. The first diode is coupled between an input output (IO) pad and a first node. The second diode is coupled to the first diode, and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. The second diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit. The first conductive structure is configured to provide a reference voltage to the first signal tap region.
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Patent Agency Ranking
公开(公告)号：US20240096873A1
公开(公告)日：2024-03-21
申请号：US18520998
申请日：2023-11-28
Inventor： Chun-Chia HSU , Tung-Heng HSIEH , Yung-Feng CHANG , Bao-Ru YOUNG , Jam-Wem LEE , Chih-Hung WANG
IPC: H01L27/02 , H01L29/06 , H01L29/861
CPC classification number: H01L27/0255 , H01L29/0692 , H01L29/861
Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.
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公开(公告)号：US20230411381A1
公开(公告)日：2023-12-21
申请号：US18360453
申请日：2023-07-27
Inventor： Tzu-Hao CHIANG , Wun-Jie LIN , Jam-Wem LEE
CPC classification number: H01L27/0248 , H01L29/0649 , H01L29/0692
Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped well in the substrate, wherein the doped well comprises a first concentration of dopants of a first type in the substrate. The semiconductor device further includes a doped region in the substrate, wherein the doped region comprises a second concentration of the dopants of the first type, the doped region extends around the doped well, and the doped region is electrically insulated from the doped well. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.
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公开(公告)号：US20230068882A1
公开(公告)日：2023-03-02
申请号：US17446192
申请日：2021-08-27
Inventor： Chia-Wei HSU , Bo-Ting CHEN , Jam-Wem LEE
IPC: H01L27/02
Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.
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公开(公告)号：US20230068649A1
公开(公告)日：2023-03-02
申请号：US17459878
申请日：2021-08-27
Inventor： Li-Wei CHU , Wun-Jie LIN , Yu-Ti SU , Ming-Fu TSAI , Jam-Wem LEE
Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.
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公开(公告)号：US20230029158A1
公开(公告)日：2023-01-26
申请号：US17936965
申请日：2022-09-30
Inventor： Chun-Chia HSU , Tung-Heng HSIEH , Yung-Feng CHANG , Bao-Ru YOUNG , Jam-Wem LEE , Chih-Hung WANG
IPC: H01L27/02 , H01L29/06 , H01L29/861
Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.
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