公开(公告)号：US20220208695A1

公开(公告)日：2022-06-30

申请号：US17192511

申请日：2021-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US11121049B2

公开(公告)日：2021-09-14

申请号：US16249756

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Amit Sureshkumar Nangia

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/16 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

公开(公告)号：US20210183717A1

公开(公告)日：2021-06-17

申请号：US16859530

申请日：2020-04-27

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/16 ,  H01L23/00

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

公开(公告)号：US12119280B2

公开(公告)日：2024-10-15

申请号：US17723439

申请日：2022-04-18

Applicant: Texas Instruments Incorporated

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/49 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/85 ,  H01L24/97

Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

公开(公告)号：US11869820B2

公开(公告)日：2024-01-09

申请号：US17810568

申请日：2022-07-01

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/00 ,  H01L23/16

CPC classification number: H01L23/16 ,  H01L24/97 ,  H01L2224/73265 ,  H01L2924/14

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

公开(公告)号：US20220415824A1

公开(公告)日：2022-12-29

申请号：US17822960

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US11387155B2

公开(公告)日：2022-07-12

申请号：US16859530

申请日：2020-04-27

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/16 ,  H01L23/00

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

公开(公告)号：US11139178B2

公开(公告)日：2021-10-05

申请号：US16653536

申请日：2019-10-15

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Siva Prakash Gurrum ,  Janakiraman Seetharaman

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/495 ,  C08G59/18 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31

Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

公开(公告)号：US20190172766A1

公开(公告)日：2019-06-06

申请号：US16249756

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Amit Sureshkumar Nangia

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

公开(公告)号：US10204842B2

公开(公告)日：2019-02-12

申请号：US15896860

申请日：2018-02-14

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/495

Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.