公开(公告)号：US20220246489A1

公开(公告)日：2022-08-04

申请号：US17723439

申请日：2022-04-18

Applicant: Texas Instruments Incorporated

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

公开(公告)号：US20230102688A1

公开(公告)日：2023-03-30

申请号：US17487318

申请日：2021-09-28

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Gregory Thomas Ostrowicki

IPC: H01L23/10 ,  H01L23/06 ,  H01L21/67

Abstract: In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.

公开(公告)号：US20210296196A1

公开(公告)日：2021-09-23

申请号：US16826047

申请日：2020-03-20

Applicant: Texas Instruments Incorporated

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

公开(公告)号：US09812384B2

公开(公告)日：2017-11-07

申请号：US15352393

申请日：2016-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/49575 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L25/074 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/73213 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.

公开(公告)号：US12119280B2

公开(公告)日：2024-10-15

申请号：US17723439

申请日：2022-04-18

Applicant: Texas Instruments Incorporated

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/49 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/85 ,  H01L24/97

Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

公开(公告)号：US20220415824A1

公开(公告)日：2022-12-29

申请号：US17822960

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US12068261B2

公开(公告)日：2024-08-20

申请号：US17822960

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/647 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48245

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US11430747B2

公开(公告)日：2022-08-30

申请号：US17192511

申请日：2021-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US20220208695A1

公开(公告)日：2022-06-30

申请号：US17192511

申请日：2021-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US20170250126A1

公开(公告)日：2017-08-31

申请号：US15352393

申请日：2016-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L25/074 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/73213 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.