公开(公告)号：US11355414B2

公开(公告)日：2022-06-07

申请号：US16586720

申请日：2019-09-27

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Daniel Lee Revier ,  Archana Venugopal

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/285

Abstract: In described examples, a circuit (e.g., an integrated circuit) includes a semiconductor substrate that includes a frontside surface and a backside surface. A circuit element is included at the frontside surface. An optional electrical insulator layer can be included adjacent to the backside surface. A distributor layer is included adjacent to the backside surface. In some examples, the distributor layer includes a distributor material that includes a matrix of cohered nanoparticles and metallic particles embedded by the cohered nanoparticles.

公开(公告)号：US20220148912A1

公开(公告)日：2022-05-12

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L21/762 ,  H01L49/02 ,  H01L27/12 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US11309388B2

公开(公告)日：2022-04-19

申请号：US16995563

申请日：2020-08-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808 ,  H01L29/66

Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

公开(公告)号：US11282807B2

公开(公告)日：2022-03-22

申请号：US16843559

申请日：2020-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Ralf Jakobskrueger Muenster ,  Sreenivasan Kalyani Koduri

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/15 ,  H01L23/495 ,  H01L23/373

Abstract: In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

公开(公告)号：US11282770B2

公开(公告)日：2022-03-22

申请号：US17039080

申请日：2020-09-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  C25D3/38

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

公开(公告)号：US11270939B2

公开(公告)日：2022-03-08

申请号：US16866255

申请日：2020-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Paul Merle Emerson ,  Benjamin Stassen Cook

IPC: H01L23/525 ,  H01L49/02 ,  H01L21/66 ,  H01L21/288 ,  H01L23/64 ,  H01L21/78

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

公开(公告)号：US11159204B2

公开(公告)日：2021-10-26

申请号：US16844861

申请日：2020-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark William Morgan ,  Swaminathan Sankaran ,  Benjamin Stassen Cook ,  Ali Djabbari ,  Lutz Albrecht Naumann

IPC: H04B5/00 ,  H02J50/10 ,  H02J50/20 ,  H02J50/40

Abstract: A removable module includes circuitry, a near field communication (NFC) coupler to provide a data signal to the circuitry, and a second NFC coupler to supply operating voltage to the circuitry.

公开(公告)号：US11145598B2

公开(公告)日：2021-10-12

申请号：US16236042

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Luigi Colombo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

公开(公告)号：US11049980B2

公开(公告)日：2021-06-29

申请号：US16668004

申请日：2019-10-30

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Benjamin Stassen Cook

IPC: H01L29/88 ,  H01L29/66 ,  H01L23/522

Abstract: In an integrated circuit, a metal-insulator-metal (MIM) diode includes: a first metallization structure level having a first metal layer; a first dielectric layer over the first metal layer; a metal contact or via on the first metal layer and extending through a portion of the first dielectric layer; and a second metallization structure level having a second metal layer; and a second dielectric layer over the second metal layer. The diode has a first electrode on the metal contact or via, a multilayer dielectric structure on the first electrode, and a second electrode between the multilayer dielectric structure and the second metal layer.

公开(公告)号：US11049836B2

公开(公告)日：2021-06-29

申请号：US15960093

申请日：2018-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David Romig ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L23/495

Abstract: A system includes a substrate; a bond pad; a wire spanning above the substrate, having a first end bonded to the bond pad and a second end extending from the bond pad to terminate in a second end thereof; and a support structure disposed on the substrate, the support structure comprising at least a side wall and extending from the substrate to terminate in an end portion spaced from the substrate to support the wire.