公开(公告)号：US12062841B2

公开(公告)日：2024-08-13

申请号：US17487023

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Harikrishna Parthasarathy

IPC: H01Q1/36 ,  H01F27/30 ,  H04B1/40

CPC classification number: H01Q1/36 ,  H01F27/30 ,  H04B1/40

Abstract: A half-duplex transceiver includes an antenna, antenna-side transformer windings coupled to the antenna, and a low-noise amplifier coupled to the antenna by the antenna-side transformer windings.

公开(公告)号：US11139791B2

公开(公告)日：2021-10-05

申请号：US16575132

申请日：2019-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Harikrishna Parthasarathy ,  Arnab Das

IPC: H03G3/30

Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

公开(公告)号：US09756572B2

公开(公告)日：2017-09-05

申请号：US14560011

申请日：2014-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram Murali ,  Sarma Gunturi ,  Jaiganesh Balakrishnan ,  Murugesh Subramaniam ,  Harikrishna Parthasarathy

IPC: H04W52/02 ,  H04W76/04 ,  H04L5/16 ,  H04L25/49 ,  H04L27/14 ,  H04B1/44

CPC classification number: H04W52/028 ,  H04B1/44 ,  H04L5/16 ,  H04L25/4902 ,  H04L27/14 ,  H04W76/28 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/168

Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.

公开(公告)号：US20140097810A1

公开(公告)日：2014-04-10

申请号：US13647156

申请日：2012-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Harikrishna Parthasarathy ,  Srinivas Venkata Veeramreddi ,  Sudhir Polarouthu ,  Baher S. Haroun

IPC: H02J1/02

CPC classification number: H02M3/1563

Abstract: As disclosed herein, two hysteresis levels, a high level a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using a set of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.

Abstract translation: 如本文所公开的，可以使用两个滞后电平（高电平低电平）来设置DC-DC转换器的输出电压的周期（和开关频率）以及转换器的输出纹波。 这两个阈值可以使用一组开关来改变。 通过控制开关的导通时间的顺序和持续时间，可以控制输出中的频谱杂散，并且可以减小感兴趣的幅度和频带。 通过对开关的控制进行随机化，可以实现额外的齿间减少。