公开(公告)号：US20150170975A1

公开(公告)日：2015-06-18

申请号：US14572891

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L21/8238 ,  H01L21/027 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L21/823475 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract translation: 一种形成集成电路的过程，该集成电路包含连接到三个有源区和/或MOS栅的细长触点，以及使用光刻冻结连接到两个有源区和/或MOS栅并直接连接到第一级互连的细长触点 用于接触蚀刻掩模的光蚀刻工艺。 一种形成集成电路的过程，该集成电路包含连接到三个有源区和/或MOS栅的细长触点，以及使用光刻冻结连接到两个有源区和/或MOS栅并直接连接到第一级互连的细长触点 用于第一级互连沟槽蚀刻掩模的光蚀刻工艺。 使用用于接触蚀刻掩模的光刻冷冻 - 光刻蚀工艺和用于第一级互连沟槽蚀刻掩模的光刻冷冻 - 光刻蚀工艺形成集成电路的工艺。

公开(公告)号：US20150170962A1

公开(公告)日：2015-06-18

申请号：US14572905

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/283 ,  H01L23/50 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

Abstract translation: 包含细长触点的集成电路，包括连接到至少三个有源区和/或MOS栅的细长触点，并且包括连接到正好两个有源区和/或MOS栅并且直接连接到第一级互连的细长触点。 一种形成包含细长触点的集成电路的过程，包括使用两个接触光刻曝光操作连接到至少三个有源区和/或MOS栅的细长触点，并且包括连接到正好两个有源区和/或 MOS门并直接连接到第一级互连。

公开(公告)号：US20140101622A1

公开(公告)日：2014-04-10

申请号：US14102086

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70125 ,  G03F7/70433

Abstract: A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration.

Abstract translation: 产生设计规则，OPC规则和优化用于集成电路布局的照明源模型以在相邻并行路径轨道之间形成短线，终止线和交叉的过程可以包括以下步骤：生成使用集合的模板结构集合 的特征设计规则，并且在每个SMO操作中对于设计规则具有不同值的模板结构集合执行多个源掩码优化（SMO）操作。 在第一实施例中，使用针对每个设计规则的预定值来运行SMO操作，跨越期望的设计规则值范围。 在第二实施例中，在条件迭代过程中执行SMO操作，其中基于迭代结果在每次迭代之后调整设计规则的值。

公开(公告)号：US20130246983A1

公开(公告)日：2013-09-19

申请号：US13887672

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Walter BLATCHFORD ,  Yong Seok CHOI ,  Thomas J. ATON

IPC: G06F17/50

CPC classification number: G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.