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公开(公告)号：US20210320093A1
公开(公告)日：2021-10-14
申请号：US17357459
申请日：2021-06-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jonathan Almeria Noquil , Makarand Ramkrishna Kulkarni
IPC: H01L25/16 , H01L23/498 , H01L23/00 , H01L23/31 , H01L23/538
Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.
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公开(公告)号：US20210082889A1
公开(公告)日：2021-03-18
申请号：US16574226
申请日：2019-09-18
Applicant: Texas Instruments Incorporated
Inventor： Jonathan Almeria Noquil , Makarand Ramkrishna Kulkarni
IPC: H01L25/16 , H01L23/498 , H01L23/538 , H01L23/31 , H01L23/00
Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.
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公开(公告)号：US20240332433A1
公开(公告)日：2024-10-03
申请号：US18193037
申请日：2023-03-30
Applicant: Texas Instruments Incorporated
Inventor： Li Jiang , Makarand Ramkrishna Kulkarni
CPC classification number: H01L29/945 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L21/76838 , H01L23/642 , H01L28/40 , H01L29/66181
Abstract: An electronic device includes a semiconductor die having a side, first conductive terminals along a first portion of the side, and second conductive terminals along a second portion of the side, a substrate having conductive features facing the first portion of the side of the semiconductor die and electrically coupled to respective ones of the first conductive terminals, a capacitor die or a ceramic capacitor having conductive capacitor terminals facing the second portion of the side of the semiconductor die and electrically coupled to respective ones of the second conductive terminals, and a package structure that at least partially encloses the semiconductor die, the substrate and the capacitor die or ceramic capacitor.
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Patent Agency Ranking
公开(公告)号：US20240071889A1
公开(公告)日：2024-02-29
申请号：US17897974
申请日：2022-08-29
Applicant: Texas Instruments Incorporated
Inventor： Naweed Anjum , Michael Gerald Amaro , Makarand Ramkrishna Kulkarni
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49838 , H01L23/49805 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48245 , H01L2224/73265
Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
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公开(公告)号：US20220384353A1
公开(公告)日：2022-12-01
申请号：US17500086
申请日：2021-10-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yiqi Tang , Rajen Manicon Murugan , Liang Wan , Makarand Ramkrishna Kulkarni , Jie Chen , Steven Alfred Kummerl
IPC: H01L23/538 , H01L23/00 , H01L21/48
Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.
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公开(公告)号：US11430720B2
公开(公告)日：2022-08-30
申请号：US16940243
申请日：2020-07-27
Applicant: Texas Instruments Incorporated
Inventor： Naweed Anjum , Michael Gerald Amaro , Makarand Ramkrishna Kulkarni
IPC: H01L23/495 , H01L23/498
Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
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公开(公告)号：US11160163B2
公开(公告)日：2021-10-26
申请号：US15816667
申请日：2017-11-17
Applicant: Texas Instruments Incorporated
Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.
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公开(公告)号：US10475786B1
公开(公告)日：2019-11-12
申请号：US16037695
申请日：2018-07-17
Applicant: Texas Instruments Incorporated
Inventor： Yiqi Tang , Rajen Manicon Murugan , Makarand Ramkrishna Kulkarni
Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.
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