公开(公告)号：US10330773B2

公开(公告)日：2019-06-25

申请号：US15184715

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

IPC: G01S7/02 ,  G01S13/34 ,  H04B15/02 ,  H04L27/10 ,  G01S7/35

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

公开(公告)号：US20240183939A1

公开(公告)日：2024-06-06

申请号：US18420133

申请日：2024-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.

公开(公告)号：US11460540B2

公开(公告)日：2022-10-04

申请号：US16208276

申请日：2018-12-03

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Sriram Murali ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G01S13/34 ,  H03D1/22 ,  G01S7/40 ,  H03D7/16 ,  H03D3/00 ,  G01S13/931

Abstract: A FMCW radar receiver includes a LO providing a chirped LO signal, an in-phase (I) channel for outputting I-data and a quadrature (Q) channel for outputting Q-data. A dynamic correction parameter generator generates IQ phase correction values (P[n]s) and IQ gain correction values (G[n]s) based on a frequency slope rate of the chirped LO signal for generating during intervals of chirps including a first sequence of P[n]s and G[n]s during a first chirp and a second sequence of P[n]s and G[n]s during a second chirp. An IQ mismatch (IQMM) correction circuit has a first IQMM input coupled to receive the I-data and a second IQMM input receiving the Q-data, and the P[n]s and G[n]s. During the first chirp the IQMM correction circuit provides first Q′-data and first I′-data and during the second chirp the IQMM correction circuit provides at least second Q′-data and second I′-data.

公开(公告)号：US20220128652A1

公开(公告)日：2022-04-28

申请号：US17572714

申请日：2022-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G06F17/14 ,  H04L27/26

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

公开(公告)号：US09967123B1

公开(公告)日：2018-05-08

申请号：US15426464

申请日：2017-02-07

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

IPC: H04L27/00 ,  H04L27/26

CPC classification number: H04L27/2615 ,  H04L27/2634

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

公开(公告)号：US12045582B2

公开(公告)日：2024-07-23

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Karthik Subburaj ,  Sujaata Ramalingam ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US11927689B2

公开(公告)日：2024-03-12

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

公开(公告)号：US20230418555A1

公开(公告)日：2023-12-28

申请号：US18335452

申请日：2023-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

IPC: G06F7/24 ,  G06F5/06

CPC classification number: G06F7/24 ,  G06F5/065 ,  G06F2207/228

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US20230275594A1

公开(公告)日：2023-08-31

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US11714603B2

公开(公告)日：2023-08-01

申请号：US17156731

申请日：2021-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

IPC: G06F7/24 ,  G06F5/06

CPC classification number: G06F7/24 ,  G06F5/065 ,  G06F2207/228

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.