公开(公告)号：US10964803B2

公开(公告)日：2021-03-30

申请号：US16194794

申请日：2018-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US09741718B2

公开(公告)日：2017-08-22

申请号：US14803759

申请日：2015-07-20

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L21/761 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US20160322263A1

公开(公告)日：2016-11-03

申请号：US15204428

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/10 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09117691B2

公开(公告)日：2015-08-25

申请号：US14101442

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

Abstract translation: 包含模拟MOS晶体管的集成电路具有用于阱的注入掩模，该掩模从栅极边缘处的两个稀释区域阻挡良好的掺杂剂，但是将沟道区域暴露于阱掺杂剂。 热驱动步骤将注入的阱掺杂物扩散到两个稀释区域上以在两个稀释区域中形成具有较低掺杂密度的连续阱。 通过使用栅极作为阻挡层将源极/漏极掺杂剂注入邻近栅极的衬底中，形成栅/漏区邻近并且使其重叠，随后使衬底退火，使得注入的源极/漏极掺杂剂提供期望的程度 栅极下的源极/漏极区的叠加。 漏极延伸掺杂剂和卤素掺杂剂不会被注入到与栅极相邻的衬底中。

公开(公告)号：US09117687B2

公开(公告)日：2015-08-25

申请号：US13663015

申请日：2012-10-29

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/761 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract translation: 包含在低电压范围内工作的第一多个MOS晶体管的集成电路和在中间电压范围内工作的第二多个MOS晶体管也可以包括高电压MOS晶体管，其操作在明显高于 低电压和中等电压范围，例如20至30伏特。 高压MOS晶体管具有闭环配置，其中漏极区域被栅极包围，栅极又被源极区域包围，使得栅极不与场氧化物重叠。 集成电路可以包括高压MOS晶体管的n沟道版本和/或高压MOS晶体管的p沟道版本。 n沟道版本和p沟道版本的注入区域与第一和第二多个MOS晶体管中的注入区域同时形成。

公开(公告)号：US09064726B2

公开(公告)日：2015-06-23

申请号：US13789477

申请日：2013-03-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/20 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract translation: 第一类型的杂质原子通过栅极和薄栅极电介质注入到在沟道区的中间点处基本上仅具有第一类型的杂质原子的沟道区，以增加第一类杂质的平均掺杂浓度 通道区域中的原子来调节晶体管的阈值电压。

公开(公告)号：US08933510B2

公开(公告)日：2015-01-13

申请号：US14142006

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Amitava Chatterjee ,  Imran Khan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823456

Abstract: An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.

Abstract translation: 可以通过将MOS晶体管和DEMOS晶体管的源/漏区相同的导电类型的掺杂剂通过MOS晶体管的栅极并通过栅极形成包含具有相同极性的MOS晶体管和DEMOS晶体管的集成电路 的DEMOS晶体管。 注入的掺杂剂从DEMOS晶体管栅极的漏极侧边缘封闭。 注入的掺杂剂在DEMOS晶体管栅极的DEMOS晶体管的扩展漏极的漂移区域内形成漏极增强区域。

公开(公告)号：US20240363748A1

公开(公告)日：2024-10-31

申请号：US18309792

申请日：2023-04-29

Applicant: Texas Instruments Incorporated

Inventor： Dhanoop Varghese ,  Henry Litzmann Edwards ,  Pinghai Hao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/66681

Abstract: Semiconductor devices including selectively doped gate electrodes are described. The semiconductor device comprises a substrate including a body region and a drift region, a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, and a gate dielectric layer on the drift region, the field relief dielectric layer laterally abutting the gate dielectric layer at a location in the drift region. The semiconductor device also includes a gate electrode having an n-doped first portion, a p-doped second portion, and an n-doped third portion. The selectively doped second portion of the gate electrode is located over an intersection between the gate dielectric layer and the field relief dielectric layer.

公开(公告)号：US09865507B2

公开(公告)日：2018-01-09

申请号：US15204428

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/423 ,  H01L27/092 ,  H01L27/10 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09842895B2

公开(公告)日：2017-12-12

申请号：US15055959

申请日：2016-02-29

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Fuchao Wang ,  Duofeng Yue

IPC: H01C1/012 ,  H01L49/02 ,  H01C17/06 ,  H01C7/00 ,  H01C17/075

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01C17/06 ,  H01C17/075 ,  Y10T29/435

Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.