公开(公告)号：US20220190148A1

公开(公告)日：2022-06-16

申请号：US17121992

申请日：2020-12-15

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Nicholas Stephen Dellas ,  Qhalid Fareed

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/04

Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

公开(公告)号：US11011515B2

公开(公告)日：2021-05-18

申请号：US15988618

申请日：2018-05-24

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Naveen Tipirneni

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/306 ,  H01L29/423 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

公开(公告)号：US20160293596A1

公开(公告)日：2016-10-06

申请号：US14673844

申请日：2015-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qhalid Fareed ,  Naveen Tipirneni

IPC: H01L27/088 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L27/0883 ,  H01L21/02241 ,  H01L21/30612 ,  H01L21/30621 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract translation: 在III-N层堆叠中包含增强型GaN FET的半导体器件包括低掺杂GaN层，在低掺杂GaN层上包括铝的阻挡层，在阻挡层上包括铟的应力层，以及帽 层包括在应力层上的铝。 栅极凹槽延伸穿过覆盖层和应力层，但不穿过阻挡层。 半导体器件通过用高温MOCVD工艺形成阻挡层而形成，通过低温MOCVD工艺形成应力层，并用低温MOCVD工艺形成覆盖层。 栅极凹部通过包括第一蚀刻步骤以去除覆盖层的两步蚀刻工艺形成，以及第二蚀刻步骤以去除应力层。

公开(公告)号：US20250063756A1

公开(公告)日：2025-02-20

申请号：US18938715

申请日：2024-11-06

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Nicholas Stephen Dellas ,  Qhalid Fareed

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

公开(公告)号：US20230411461A1

公开(公告)日：2023-12-21

申请号：US17806959

申请日：2022-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Qhalid Fareed

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/0254

Abstract: A semiconductor device is described herein. The semiconductor device comprises a silicon substrate layer. The semiconductor device comprises a first semiconductor layer comprising a gallium nitride layer, the first semiconductor layer disposed over the silicon substrate layer. The semiconductor device comprises a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising an aluminum gallium nitride layer. The semiconductor device comprises a first drain contact extending through the second semiconductor layer and extending into the first semiconductor layer.

公开(公告)号：US20230197784A1

公开(公告)日：2023-06-22

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/0653

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20210242200A1

公开(公告)日：2021-08-05

申请号：US17234385

申请日：2021-04-19

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Naveen Tipirneni

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/306

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

公开(公告)号：US09590086B2

公开(公告)日：2017-03-07

申请号：US15090689

申请日：2016-04-05

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Asad Mahmood Haider

IPC: H01L29/06 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L29/15 ,  H01L29/51 ,  H01L29/10

CPC classification number: H01L21/02505 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7781 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/78

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract translation: 制造用于晶体管的多层外延缓冲层堆叠的方法包括在衬底上沉积缓冲层。 第一空穴IIIA-N层被沉积在衬底上，然后在第一空穴IIIA-N层上沉积第一基本无空隙的IIIA-N层。 第一高粗糙度组IIIA-N层沉积在第一基本无空隙的IIIA-N族第一层上，并且第一基本上平滑的IIIA-N层沉积在第一高粗糙度IIIA-N层上。 然后将至少一个IIIA-N族表面层沉积在第一基本上平滑的IIIA-N层上。