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    Contact pad fabrication process for a semiconductor product
    11.
    发明授权
    Contact pad fabrication process for a semiconductor product 有权

    公开(公告)号：US12170256B2

    公开(公告)日：2024-12-17

    申请号：US17459849

    申请日：2021-08-27

    Applicant: Texas Instruments Incorporated

    Inventor： Sudtida Lavangkul ,  Yung Shan Chang

    IPC: H01L23/48 ,  H01L21/311 ,  H01L21/44 ,  H01L23/00 ,  H01L23/532

    Abstract: A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.

    Integrated fluxgate device
    13.
    发明授权
    Integrated fluxgate device 有权

    公开(公告)号：US10978448B2

    公开(公告)日：2021-04-13

    申请号：US15003856

    申请日：2016-01-22

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

    IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

    CONTACT PAD FABRICATION PROCESS FOR A SEMICONDUCTOR PRODUCT
    17.
    发明申请
    CONTACT PAD FABRICATION PROCESS FOR A SEMICONDUCTOR PRODUCT 有权

    公开(公告)号：US20230061951A1

    公开(公告)日：2023-03-02

    申请号：US17459849

    申请日：2021-08-27

    Applicant: Texas Instruments Incorporated

    Inventor： Sudtida Lavangkul ,  Yung Shan Chang

    IPC: H01L23/00 ,  H01L23/532 ,  H01L21/311

    Abstract: A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.

    METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING
    18.
    发明申请
    METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING 有权

    公开(公告)号：US20230017047A1

    公开(公告)日：2023-01-19

    申请号：US17953301

    申请日：2022-09-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

    IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

    Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

    LAYOUTS FOR INTERLEVEL CRACK PREVENTION IN FLUXGATE TECHNOLOGY MANUFACTURING
    19.
    发明申请
    LAYOUTS FOR INTERLEVEL CRACK PREVENTION IN FLUXGATE TECHNOLOGY MANUFACTURING 审中-公开

    公开(公告)号：US20190331742A1

    公开(公告)日：2019-10-31

    申请号：US16503660

    申请日：2019-07-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sudtida Lavangkul ,  Sopa Chevacharoenkul

    IPC: G01R33/04

    Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.

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