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公开(公告)号：US09793918B2
公开(公告)日：2017-10-17
申请号：US14814617
申请日：2015-07-31
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan Rangachari , Desmond Pravin Martin Fernandes , Rakesh Channabasappa Yaraduyathinahalli
Abstract: A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.
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公开(公告)号：US20160277007A1
公开(公告)日：2016-09-22
申请号：US14664078
申请日：2015-03-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Sachin Bharadwaj , Sundarrajan Rangachari
IPC: H03H11/04
CPC classification number: H03H11/04 , H03H17/0275 , H03H17/028 , H03H17/0642
Abstract: Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the example embodiments, the input samples are upsampled by a factor N in an upsampler followed by a filter which then goes through a linear interpolator. The filter cleans the spectral images of the signal created due to the upsampling operation.
Abstract translation: 本文公开的可变分数速率数字重采样的系统和方法的示例实施例实现可变速率转换。 在示例实施例中，输入样本在上采样器中由因子N上采样，随后是滤波器，滤波器然后经过线性内插器。 滤波器清除由于上采样操作而产生的信号的光谱图像。
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公开(公告)号：US20160127161A1
公开(公告)日：2016-05-05
申请号：US14528660
申请日：2014-10-30
Applicant: Texas Instruments Incorporated
Inventor： Sriram Murali , Indu Prathapan , Pankaj Gupta , Zahir Ibrahim Parkar , Sundarrajan Rangachari
IPC: H04L27/156 , H04L27/38 , H04L27/34 , H04L27/14
CPC classification number: H04L27/1566 , H04L27/3455 , H04W52/0229 , Y02D70/00
Abstract: A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message.
Abstract translation: 公开了可以是FM接收机的一部分的气象带接收机。 使用正交匹配滤波器电路检测警报分组传输中的FSK编码数据单元。 从警报包传输中捕获至少一个FSK编码的数据单元。 从FSK编码数据单元提取软量化比特。 软量化位保存到存储器中，用于恢复警报消息。 可以在恢复警报消息之前组合来自两个或更多个FSK编码数据单元的软量化比特。
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公开(公告)号：US11422586B1
公开(公告)日：2022-08-23
申请号：US17488559
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： Aswath Vs , Sundarrajan Rangachari , Sarma Sundareswara Gunturi , Sanjay Pennam
Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.
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公开(公告)号：US11171674B2
公开(公告)日：2021-11-09
申请号：US17022871
申请日：2020-09-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan , Sriram Murali , Sundarrajan Rangachari , Yeswanth Guntupalli
Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.
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Patent Agency Ranking
公开(公告)号：US20210148974A1
公开(公告)日：2021-05-20
申请号：US16863906
申请日：2020-04-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G01R31/3177 , G06F1/08
Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.
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公开(公告)号：US10935602B2
公开(公告)日：2021-03-02
申请号：US15973257
申请日：2018-05-07
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan Rangachari , Saket Jalan
IPC: G01R31/319 , G01R31/317 , G01R31/3177
Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.
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公开(公告)号：US10812091B2
公开(公告)日：2020-10-20
申请号：US16837537
申请日：2020-04-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sundarrajan Rangachari , Sriram Murali , Sanjay Pennam
Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.
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公开(公告)号：US20200153444A1
公开(公告)日：2020-05-14
申请号：US16680046
申请日：2019-11-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.
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公开(公告)号：US10651836B1
公开(公告)日：2020-05-12
申请号：US16281622
申请日：2019-02-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.
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