公开(公告)号：US20190205508A1

公开(公告)日：2019-07-04

申请号：US16188560

申请日：2018-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deepak Kumar PODDAR ,  Mihir MODY ,  Veeramanikandan RAJU ,  Jason A.T. JONES

IPC: G06F21/16 ,  G06F15/18 ,  G06N3/04

CPC classification number: G06F21/16 ,  G06N3/0472 ,  G06N20/00

Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

公开(公告)号：US20230102099A1

公开(公告)日：2023-03-30

申请号：US17563398

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan RAJU ,  Sudhakar SURENDRAN ,  Anand Kumar G

IPC: G06F11/14 ,  G06F11/07 ,  G06F13/40 ,  G06F13/16 ,  G06F21/60

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

公开(公告)号：US20230091498A1

公开(公告)日：2023-03-23

申请号：US17482676

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan RAJU ,  Anand Kumar G ,  Prachi MISHRA

IPC: G06F12/10 ,  G06F13/10

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

公开(公告)号：US20220269225A1

公开(公告)日：2022-08-25

申请号：US17409029

申请日：2021-08-23

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan RAJU ,  Anand Kumar G

IPC: G05B9/02 ,  G06F11/14 ,  G06F13/20 ,  G06F9/4401

Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.

公开(公告)号：US20210203979A1

公开(公告)日：2021-07-01

申请号：US16866647

申请日：2020-05-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aishwarya DUBEY ,  Shashank DABRAL ,  Veeramanikandan RAJU

IPC: H04N19/557 ,  H04N19/577 ,  H04N19/567 ,  G01S17/86 ,  G01S17/89

Abstract: Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.

公开(公告)号：US20200327260A1

公开(公告)日：2020-10-15

申请号：US16865067

申请日：2020-05-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan RAJU

IPC: G06F21/88 ,  G06F21/57 ,  H04W4/02 ,  H04L29/12 ,  H04W4/70 ,  H04W12/12

Abstract: An end-user computing device can include a theft detector that maintains a registered host device list containing identifiers of at least one registered host device. The theft detector can have root access to operations of the end-user device and the theft detector can provides a secure reboot request in response to detecting a possible theft condition. The end-user computing device can also include a boot loader that executes a secure reboot of the end-user device in response to a secure reboot request from the theft detector. The secure reboot of the end-user device resets the end-user device to prevent access to the end-user device.