公开(公告)号：US11704154B2

公开(公告)日：2023-07-18

申请号：US17359749

申请日：2021-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  William Cronin Wallace ,  Pratheesh Gangadhar Thalakkal Kottilaveedu ,  David Alston Lide

IPC: G06F9/48 ,  G06F13/28 ,  G06F13/40 ,  G06F16/9035 ,  G06F9/52 ,  G06F9/50 ,  G06F1/06 ,  G06F13/20 ,  G06F9/448 ,  G06F11/10 ,  H04L1/00

CPC classification number: G06F9/4881 ,  G06F1/06 ,  G06F9/448 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5038 ,  G06F9/52 ,  G06F11/1004 ,  G06F13/20 ,  G06F13/28 ,  G06F13/4068 ,  G06F16/9035 ,  H04L1/0041 ,  G06F2209/503 ,  G06F2209/5012

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

公开(公告)号：US11290099B2

公开(公告)日：2022-03-29

申请号：US17066660

申请日：2020-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  Martin Staebler ,  William Cronin Wallace

IPC: G06F11/07 ,  H03K7/08 ,  H02P3/18 ,  H03K19/00

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

公开(公告)号：US10970074B2

公开(公告)日：2021-04-06

申请号：US16424913

申请日：2019-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  William Cronin Wallace ,  David Alston Lide ,  Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu

IPC: G06F9/30 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/48 ,  G06F30/34

Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.