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公开(公告)号：US10389281B2
公开(公告)日：2019-08-20
申请号：US15299063
申请日：2016-10-20
Applicant: Texas Instruments Incorporated
Inventor： Martin Staebler , Ferdinand von Molo
Abstract: A sort buffer includes a phase sector determination circuit, a phase sector update circuit, and a phase sector completion circuit. The phase sector determination circuit is configured to determine a phase sector corresponding to a phase of a first sine and cosine sample pair received from an encoder or resolver. The phase sector update circuit is configured to determine whether a second sine and cosine sample pair corresponding to the phase sector is stored in a lookup table (LUT) and, in response to a determination that a second sine and cosine sample pair corresponding to the phase sector is not stored in the LUT, store the first sine and cosine sample pair in the LUT. The phase sector completion circuit is configured to determine whether the LUT has stored, for each of a plurality of phase sectors, a corresponding sine and cosine sample pair.
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公开(公告)号：US12009769B2
公开(公告)日：2024-06-11
申请号：US18054974
申请日：2022-11-14
Applicant: Texas Instruments Incorporated
Inventor： Navaneeth Kumar Narayanasamy , Martin Staebler
Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.
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公开(公告)号：US20220074794A1
公开(公告)日：2022-03-10
申请号：US17015277
申请日：2020-09-09
Applicant: Texas Instruments Incorporated
Inventor： Navaneeth Kumar Narayanasamy , Martin Staebler
Abstract: In described examples, a measurement circuit includes an isolated power supply that generates an output signal in response to an input signal. A signal processing circuit is coupled to the isolated power supply and generates a first signal in response to a sense signal. A load manipulator circuit is coupled to the signal processing circuit and the isolated power supply. The load manipulator circuit receives the first signal. A detect circuit is coupled to the isolated power supply and generates a second signal in response to the input signal.
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公开(公告)号：US10812060B2
公开(公告)日：2020-10-20
申请号：US16424862
申请日：2019-05-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , Martin Staebler , William Cronin Wallace
Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.
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公开(公告)号：US11792051B2
公开(公告)日：2023-10-17
申请号：US17352663
申请日：2021-06-21
Applicant: Texas Instruments Incorporated
Inventor： Sadia Arefin Khan , Anant Shankar Kamath , Martin Staebler , Vikas Kumar Thawani
IPC: H04L25/02 , H02K11/33 , H03K19/0175 , H03K19/003 , H02P27/08
CPC classification number: H04L25/0266 , H02K11/33 , H02P27/08 , H03K19/00323 , H03K19/017509 , H03K19/017545
Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.
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Patent Agency Ranking
公开(公告)号：US11704276B2
公开(公告)日：2023-07-18
申请号：US17748302
申请日：2022-05-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kristen N. Mogensen , Matthieu Chevrier , Martin Staebler
IPC: G06F13/42 , G06F13/12 , G06F13/374
CPC classification number: G06F13/4291 , G06F13/122 , G06F13/374
Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.
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公开(公告)号：US11579022B2
公开(公告)日：2023-02-14
申请号：US17015277
申请日：2020-09-09
Applicant: Texas Instruments Incorporated
Inventor： Navaneeth Kumar Narayanasamy , Martin Staebler
Abstract: In described examples, a measurement circuit includes an isolated power supply that generates an output signal in response to an input signal. A signal processing circuit is coupled to the isolated power supply and generates a first signal in response to a sense signal. A load manipulator circuit is coupled to the signal processing circuit and the isolated power supply. The load manipulator circuit receives the first signal. A detect circuit is coupled to the isolated power supply and generates a second signal in response to the input signal.
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公开(公告)号：US20220209695A1
公开(公告)日：2022-06-30
申请号：US17137598
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Navaneeth Kumar Narayanasamy , Martin Staebler
Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.
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公开(公告)号：US11341081B1
公开(公告)日：2022-05-24
申请号：US17197945
申请日：2021-03-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kristen N. Mogensen , Matthieu Chevrier , Martin Staebler
IPC: G06F13/42 , G06F13/12 , G06F13/374
Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.
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公开(公告)号：US20230072415A1
公开(公告)日：2023-03-09
申请号：US18054974
申请日：2022-11-14
Applicant: Texas Instruments Incorporated
Inventor： Navaneeth Kumar Narayanasamy , Martin Staebler
Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.
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