公开(公告)号：US09911753B2

公开(公告)日：2018-03-06

申请号：US15257138

申请日：2016-09-06

Applicant: Toshiba Memory Corporation

Inventor： Masayuki Kitamura ,  Atsuko Sakata ,  Satoshi Wakatsuki ,  Takeshi Ishizaki ,  Daisuke Ikeno ,  Tomotaka Ariga

IPC: H01L27/115 ,  H01L21/48 ,  H01L23/498 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/486 ,  H01L23/49827 ,  H01L27/11556 ,  H01L28/00 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.

公开(公告)号：US09793293B1

公开(公告)日：2017-10-17

申请号：US15461509

申请日：2017-03-17

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Shinichi Nakao ,  Yasuhito Yoshimizu ,  Kouji Matsuo ,  Kei Watanabe ,  Atsuko Sakata

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/321 ,  H01L21/283

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/32105 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed; a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and a first separation region provided in the stacked body and extending in a first direction. The stacked body includes a memory cell array and a staircase portion arranged in the first direction, the memory cell array including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged along the first direction. The first separation region includes a first portion and a second portion in the staircase portion, the first portion having a first width in a second direction crossing the first direction, and the second portion having a second width in the second direction. The second width is narrower than the first width.

公开(公告)号：US10892300B2

公开(公告)日：2021-01-12

申请号：US16570230

申请日：2019-09-13

Applicant: Toshiba Memory Corporation

Inventor： Takanori Usami ,  Takeshi Ishizaki ,  Ryohei Kitao ,  Katsuyoshi Komatsu ,  Takeshi Iwasaki ,  Atsuko Sakata

IPC: H01L27/24 ,  H01L27/22

Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).

公开(公告)号：US10700272B2

公开(公告)日：2020-06-30

申请号：US16117718

申请日：2018-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro Katono ,  Takeshi Ishizaki ,  Atsuko Sakata

IPC: H01L45/00

Abstract: According to one embodiment, the semiconductor memory device includes a first electrode, a first material layer, including a first material, located on the first electrode, a second material, surrounded by the first material of the first material layer, including a phase change material, and a second electrode provided on the first material.

公开(公告)号：US20200090931A1

公开(公告)日：2020-03-19

申请号：US16283609

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Yuya MATSUBARA ,  Masayuki Kitamura ,  Atsuko Sakata

IPC: H01L21/02 ,  H01L21/285 ,  C23C16/50 ,  C23C16/30 ,  C23C16/52 ,  C23C16/32

Abstract: A substrate processing apparatus includes a chamber to accommodate a substrate. The apparatus includes a stage to support the substrate in the chamber. The apparatus includes an electrode disposed above the stage and containing aluminum. The electrode generates plasma from gas supplied into the chamber to form a first film on the substrate by the plasma. The apparatus further includes a second film formed on a surface of the electrode and containing aluminum and fluorine or containing aluminum and oxygen.

公开(公告)号：US10170494B2

公开(公告)日：2019-01-01

申请号：US15048120

申请日：2016-02-19

Applicant: Toshiba Memory Corporation

Inventor： Takeshi Ishizaki ,  Atsuko Sakata ,  Satoshi Wakatsuki

IPC: H01L27/11 ,  H01L27/11582 ,  H01L49/02

Abstract: According to one embodiment, a semiconductor device includes an underlying metal film and a metal film. The underlying metal film is a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %, a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or a tungsten film. The metal film is provided on the underlying metal film and in contact with the underlying metal film. The metal film contains at least one of tungsten and molybdenum, and has a main orientation of (100) or (111).