公开(公告)号：US10566280B2

公开(公告)日：2020-02-18

申请号：US16103106

申请日：2018-08-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi Wakatsuki ,  Masayuki Kitamura ,  Takeshi Ishizaki ,  Hiroshi Itokawa ,  Daisuke Ikeno ,  Kei Watanabe ,  Atsuko Sakata

IPC: H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/532 ,  H01L21/28

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.

公开(公告)号：US10269825B2

公开(公告)日：2019-04-23

申请号：US15258275

申请日：2016-09-07

Applicant: Toshiba Memory Corporation

Inventor： Satoshi Wakatsuki ,  Atsuko Sakata ,  Daisuke Ikeno

IPC: H01L27/1157 ,  H01L27/11582

Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.

公开(公告)号：US10833265B2

公开(公告)日：2020-11-10

申请号：US16556057

申请日：2019-08-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke Ikeno ,  Akihiro Kajita ,  Atsuko Sakata

IPC: H01L45/00 ,  H01L27/24

Abstract: According to one embodiment, a storage device includes a first conductive layer, a second conductive layer, a resistance-variable layer, between the first conductive layer and the second conductive layer, that includes germanium, antimony, and tellurium, a first layer, between the resistance-variable layer and the first conductive layer, that includes carbon, a second layer, between the resistance-variable layer and the second conductive layer, that includes carbon, a third layer, between the resistance-variable layer and the first layer, that includes at least one of tungsten nitride or tungsten carbide, and a fourth layer, between the resistance-variable layer and the second layer, that includes at least one of tungsten nitride or tungsten carbide.

公开(公告)号：US10763122B2

公开(公告)日：2020-09-01

申请号：US15695918

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Soichi Yamazaki ,  Kazuhito Furumoto ,  Kosuke Horibe ,  Keisuke Kikutani ,  Atsuko Sakata ,  Junichi Wada ,  Toshiyuki Sasaki

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/11582 ,  H01L27/1157

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.

公开(公告)号：US10541250B2

公开(公告)日：2020-01-21

申请号：US15195482

申请日：2016-06-28

Applicant: Toshiba Memory Corporation

Inventor： Ryohei Kitao ,  Atsuko Sakata ,  Takeshi Ishizaki ,  Satoshi Wakatsuki ,  Shinichi Nakao ,  Shunsuke Ochiai ,  Kei Watanabe

IPC: H01L27/00 ,  H01L27/11582 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

公开(公告)号：US10134673B2

公开(公告)日：2018-11-20

申请号：US15449654

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masayuki Kitamura ,  Atsuko Sakata

IPC: H01L29/40 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes a contact plug which includes a barrier metal layer provided in the insulating film, and a plug material layer provided in the insulating film, the barrier metal layer disposed between the plug material layer and the insulating film. The barrier metal layer includes at least a first layer including a first metal element and nitrogen, and a second layer including a second metal element different from the first metal element, and nitrogen.

公开(公告)号：US09905462B2

公开(公告)日：2018-02-27

申请号：US14985969

申请日：2015-12-31

Applicant: Toshiba Memory Corporation

Inventor： Atsuko Sakata ,  Takeshi Ishizaki ,  Shinya Okuda ,  Kei Watanabe ,  Masayuki Kitamura ,  Satoshi Wakatsuki ,  Daisuke Ikeno ,  Junichi Wada ,  Hirotaka Ogihara

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/3065 ,  H01L29/788

CPC classification number: H01L21/76879 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76864 ,  H01L27/11582 ,  H01L29/7881

Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.

公开(公告)号：US09754793B2

公开(公告)日：2017-09-05

申请号：US15376336

申请日：2016-12-12

Applicant: Toshiba Memory Corporation

Inventor： Shinichi Nakao ,  Shunsuke Ochiai ,  Yusuke Oshiki ,  Kei Watanabe ,  Mitsuhiro Omura ,  Kosuke Horibe ,  Atsuko Sakata ,  Junichi Wada ,  Soichi Yamazaki ,  Masayuki Kitamura ,  Yuya Matsubara

IPC: H01L21/336 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11582

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11582 ,  H01L28/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.

公开(公告)号：US11177135B2

公开(公告)日：2021-11-16

申请号：US16283570

申请日：2019-02-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuya Matsubara ,  Masayuki Kitamura ,  Atsuko Sakata

IPC: H01L21/3065 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3213

Abstract: A mask member contains tungsten (W), boron (B), and carbon (C). The mask member includes a first portion in contact with a process film, the first portion, in which the terms of the composition ratio, which correspond to boron and carbon, are larger than the term of the composition ratio, which corresponds to tungsten, and a second portion in which the term of the composition ratio, which corresponds to tungsten, is larger than the terms of the composition ratio, which correspond to carbon and boron.

公开(公告)号：US11004804B2

公开(公告)日：2021-05-11

申请号：US16294984

申请日：2019-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi Wakatsuki ,  Masayuki Kitamura ,  Atsuko Sakata

IPC: H01L23/00 ,  H01L27/11568 ,  H01L27/11521 ,  H01L29/06

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.