公开(公告)号：US10262729B2

公开(公告)日：2019-04-16

申请号：US15696116

申请日：2017-09-05

申请人： TOSHIBA MEMORY CORPORATION

发明人： Kunifumi Suzuki ,  Kazuhiko Yamamoto

IPC分类号： G11C13/00 ,  H01L27/24 ,  H01L45/00

摘要： A storage device includes a first conductive layer, a second conductive layer, a first variable resistance layer, and a control circuit. The control circuit is configured to apply a first voltage between the first conductive layer and the second conductive layer for a first time and apply a second voltage less than the first voltage for a second time longer than the first time after the application of the first voltage when the first variable resistance layer is in a first high resistance state. The control circuit is further configured to apply the first voltage between the first conductive layer and the second conductive layer and apply a third voltage less than the second voltage between the first conductive layer and the second conductive layer after the application of the first voltage when the first variable resistance layer is in a first low resistance state.

公开(公告)号：US09893280B2

公开(公告)日：2018-02-13

申请号：US14793891

申请日：2015-07-08

申请人： Toshiba Memory Corporation

发明人： Kunifumi Suzuki ,  Junji Tominaga

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1233

摘要： A memory device according to an embodiment includes an insulating layer containing silicon, an interface layer provided on the insulating layer and containing a chalcogenide compound of a transition metal, and a conductive layer provided on the interface layer, containing antimony or bismuth, and having a superlattice structure.

公开(公告)号：US10424731B2

公开(公告)日：2019-09-24

申请号：US14808584

申请日：2015-07-24

申请人： Toshiba Memory Corporation

发明人： Kunifumi Suzuki ,  Kazuhiko Yamamoto

IPC分类号： H01L45/00 ,  H01L27/24

摘要： According to one embodiment, a memory device includes a first electrode; a variable resistance layer provided on the first electrode, the variable resistance layer including a chalcogenide compound having a crystal structure; and a second electrode provided on the variable resistance layer. The variable resistance layer includes a first region covering one of an upper surface of the first electrode or a lower surface of the second electrode, and a second region, a concentration of the chemical element being lower in the second region than in the first region.

公开(公告)号：US10217514B2

公开(公告)日：2019-02-26

申请号：US16011923

申请日：2018-06-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Kunifumi Suzuki ,  Kazuhiko Yamamoto

IPC分类号： G11C13/00

摘要： According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.

公开(公告)号：US10068642B1

公开(公告)日：2018-09-04

申请号：US15696118

申请日：2017-09-05

申请人： TOSHIBA MEMORY CORPORATION

发明人： Kunifumi Suzuki ,  Kazuhiko Yamamoto

IPC分类号： G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1616

摘要： A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third conductive layer, (ii) start a second application of the first voltage between a second conductive layer and the third conductive layer after a lapse of a first delay time since the start of the first application of the first voltage, and (iii) start an application of a second voltage, which is smaller than the first voltage, between the first conductive layer and the third conductive layer after a lapse of a second delay time since the start of the second application of the first voltage between the second conductive layer and the third conductive layer.

公开(公告)号：US09779812B1

公开(公告)日：2017-10-03

申请号：US15269523

申请日：2016-09-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Kunifumi Suzuki ,  Kazuhiko Yamamoto

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/77

摘要： According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to transition a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse.