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    Semiconductor memory device having preamplifier with improved data propagation speed
    11.
    发明授权
    Semiconductor memory device having preamplifier with improved data propagation speed 失效
    具有提高数据传播速度的前置放大器的半导体存储器件

    公开(公告)号：US06714471B2

    公开(公告)日：2004-03-30

    申请号：US10270653

    申请日：2002-10-16

    申请人： Takashi Kono

    发明人： Takashi Kono

    IPC分类号： G11C700

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4096 ,  G11C2207/107

    摘要： A preamplifier includes an amplifier circuit amplifying a signal level of read data, a latency shifter outputting the read data onto a data line pair in response to an internal signal determining a timing of outputting the read data onto the data bus pair, and a driver outputting the read data onto the data bus pair. The amplifier circuit receives the internal signal and outputs the read data onto the data line pair while bypassing the latency shifter when the internal signal is already at high level at the timing when the signal level of the read data is amplified. As a result, a semiconductor memory device can speed up propagation of the read data from the preamplifier onto the data bus pair in a high frequency operation.

    摘要翻译： 前置放大器包括：放大电路，放大读取数据的信号电平;延迟移位器响应于确定将读出的数据输出到数据总线对上的定时的内部信号，将读出的数据输出到数据线对;以及驱动器输出 将数据读取到数据总线上。 当读取数据的信号电平被放大的定时，当内部信号已经处于高电平时，放大器电路接收内部信号并将读取的数据输出到数据线对上，同时绕过等待时间移位器。 结果，半导体存储器件可以在高频操作中加速读取数据从前置放大器传播到数据总线对上。

    Semiconductor memory device including clock generation circuit
    12.
    发明授权
    Semiconductor memory device including clock generation circuit 失效
    半导体存储器件包括时钟发生电路

    公开(公告)号：US06707758B2

    公开(公告)日：2004-03-16

    申请号：US10234240

    申请日：2002-09-05

    申请人： Takashi Kono

    发明人： Takashi Kono

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/107

    摘要： A DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency from the first and second internal clocks on the basis of an internal signal. A repeater recovers signal levels of the third and fourth internal clocks and outputs the third and fourth internal clocks as DLL clocks. The data output circuit takes in read data using the DLL clocks outputted from the repeater, and outputs the read data to an outside in a half cycle synchronously with the DLL clocks. In this way, a circuit area of a semiconductor memory device can be reduced by generating the DLL clocks in a prior stage to the data output circuit.

    摘要翻译： DLL电路产生从外部时钟延迟适当量的第一和第二内部时钟，并且产生第三和第四内部时钟，其能够在基于内部信号的第一和第二内部时钟的CAS等待时间之后驱动数据输出电路 。 中继器恢复第三和第四内部时钟的信号电平，并将第三和第四内部时钟作为DLL时钟输出。 数据输出电路使用从中继器输出的DLL时钟，读取数据，并将读出的数据以与DLL时钟同步的半周期的形式输出到外部。 以这种方式，可以通过在数据输出电路的前一级生成DLL时钟来减少半导体存储器件的电路面积。

    Semiconductor memory device capable of performing stable sensing operation even under low power supply voltage environment
    13.
    发明授权
    Semiconductor memory device capable of performing stable sensing operation even under low power supply voltage environment 失效
    半导体存储器件即使在低电源电压环境下也能够执行稳定的感测操作

    公开(公告)号：US06392944B1

    公开(公告)日：2002-05-21

    申请号：US09985283

    申请日：2001-11-02

    申请人： Takashi Kono

    发明人： Takashi Kono

    IPC分类号： G11C708

    CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4074

    摘要： A semiconductor memory device includes two power feed lines. An overdriving scheme is applied to one of the power feed lines in the sensing amplifying operation, and no overdriving scheme is applied to the other power feed line in the sensing operation. According to the overdriving scheme, the power feed line is overdriven to a potential level higher than a potential corresponding high level data stored in a memory cell. Thus, the overdriving of the power feed line is applied as an auxiliary function to prevent application of an excess potential to a memory cell capacitor. Such a semiconductor memory device can be achieved that improves both the speed of sensing amplifying operation and the reliability of memory cell capacitors, while conforming to low voltage operation requirement.

    摘要翻译： 半导体存储器件包括两个馈电线。 在感测放大操作中，对一个馈电线路施加过驱动方案，并且在感测操作中不将过驱动方案应用于另一馈电线路。 根据过驱动方案，馈电线被过驱动到高于存储在存储单元中的电位对应的高电平数据的电位电平。 因此，作为辅助功能施加供电线的过驱动，以防止对存储单元电容器施加过多的电位。 可以实现这样的半导体存储器件，其在符合低电压操作要求的同时，提高了感测放大操作的速度和存储单元电容器的可靠性。

    Semiconductor device having an internal voltage generating circuit
    14.
    发明授权
    Semiconductor device having an internal voltage generating circuit 失效
    具有内部电压产生电路的半导体器件

    公开(公告)号：US06297624B1

    公开(公告)日：2001-10-02

    申请号：US09258159

    申请日：1999-02-26

    申请人： Katsuyoshi Mitsui ,  Kiyohiro Furutani ,  Takashi Kono

    发明人： Katsuyoshi Mitsui ,  Kiyohiro Furutani ,  Takashi Kono

    IPC分类号： G05F316

    CPC分类号： G05F1/465

    摘要： An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.

    摘要翻译： 内部电源电路从外部电源电压产生内部电源电压。 电压电平控制电路控制由内部电源电路产生的内部电源电压的电压电平和温度特性。 内部电源电路在低温区域产生具有负温度或零温度特性的内部电源电压，在高温区域产生正温度特性。 电压电平控制电路包括优化用于驱动读出放大器电路的感测电源线稳定电容的电容值的结构，确定内部电源电路的外部电源电压的最低可操作区域的电平转换电路，或 一个在上电时强制运行内部降压转换器的结构。 以小的占用面积和低的电流消耗稳定地产生期望的内部电源电压。

    Semiconductor device capable of suppressing transient variation in level of internal power supply potential
    15.
    发明授权
    Semiconductor device capable of suppressing transient variation in level of internal power supply potential 有权
    能够抑制内部电源电位的电平的瞬态变化的半导体装置

    公开(公告)号：US06232824B1

    公开(公告)日：2001-05-15

    申请号：US09440553

    申请日：1999-11-15

    申请人： Takashi Kono

    发明人： Takashi Kono

    IPC分类号： G05F110

    CPC分类号： G11C5/147 ,  G11C11/4074

    摘要： First and second buffer circuits generate first and second reference potentials. A switching circuit selects a first reference potential as a reference potential while a sense operation is not performed and selects a lower second reference potential while the sense operation is performed. A buffer circuit is controlled such that a through current increases only for a predetermined time period at a initiation and a termination of the sense operation.

    摘要翻译： 第一和第二缓冲电路产生第一和第二参考电位。 切换电路在不执行感测操作的同时选择第一参考电位作为参考电位，并且在执行感测操作时选择较低的第二参考电位。 控制缓冲电路，使得通过电流仅在感测操作的启动和终止期间增加预定时间段。

    Circuit for adjusting a voltage level in a semiconductor device
    16.
    发明授权
    Circuit for adjusting a voltage level in a semiconductor device 失效
    用于调整半导体器件中的电压电平的电路

    公开(公告)号：US6121806A

    公开(公告)日：2000-09-19

    申请号：US166909

    申请日：1998-10-06

    申请人： Takashi Kono ,  Takayuki Miyamoto ,  Katsuyoshi Mitsui ,  Shinichi Jinbo

    发明人： Takashi Kono ,  Takayuki Miyamoto ,  Katsuyoshi Mitsui ,  Shinichi Jinbo

    IPC分类号： G11C5/14 ,  G11C29/02 ,  G11C29/50 ,  H03K3/286

    CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C5/143 ,  G11C5/147 ,  G11C11/401 ,  G11C2029/5004

    摘要： A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.

    摘要翻译： 一种电平调节电路，用于控制提供给诸如半导体器件的负载的电压，其包括电压电平检测电路，用于产生要输出到电压电平检测电路的一对参考电位值的参考电位产生电路，以及 用于绘制提供给负载的电压的监视器焊盘，其中分别使用参考电位值与电压进行比较，从而输出用于开始电压供应的信号和用于停止在通常情况下提供电压的信号 使用条件; 并且电压电平检测电路将参考电位值与电压或其他参考电位值中的任一个与测试条件下的一次电压进行比较，从而可以精确地调整参考电位产生电路以改变参考值 将电压值置于负载运行允许范围内的电位值。

    Oil retaining bearing unit and motor having oil retaining bearing unit
    19.
    发明授权
    Oil retaining bearing unit and motor having oil retaining bearing unit 失效
    油保持轴承单元和电机具有止油轴承单元

    公开(公告)号：US5810481A

    公开(公告)日：1998-09-22

    申请号：US852246

    申请日：1997-05-06

    申请人： Katsutoshi Nii ,  Makoto Kondoh ,  Takashi Kono ,  Yoshihiro Sato ,  Seiichiro Terashima

    发明人： Katsutoshi Nii ,  Makoto Kondoh ,  Takashi Kono ,  Yoshihiro Sato ,  Seiichiro Terashima

    IPC分类号： F16C17/10 ,  F16C33/10 ,  G11B19/20 ,  F16C32/06

    CPC分类号： F16C17/10 ,  F16C33/103 ,  G11B19/2009 ,  F16C2370/12

    摘要： Oil retaining bearing members 2a and 2b for supporting a rotative shaft 1 are arranged in a bearing housing 7 with an interval. The bearing housing 7 has a bottom portion, one end being opened and another end being closed. A porous spacer 3 for supplying a lubrication oil is closely inserted between the oil retaining bearings 2a and 2b. An oil thrower 8 is arranged at an upper portion of the bearing housing 7 and a thrust bearing 5 is arranged at a lower portion. The open end of the bearing housing 7 is arranged on the upper portion and the another end of the bearing housing 7 is arranged on the lower portion of the bearing housing 7, and state a lubrication oil 4a is enclosed in the housing to immerse a part of the porous spacer 3 to some degree. The pore diameter of the porous spacer 3 is larger than that of the oil retaining bearings 2a and 2b. By utilizing capillary tube action in by the porous spacer 3, the lubrication oil 4a is supplied to the oil retaining bearing 2a. Accordingly, an oil retaining bearing unit having an excellent performance and a superior mass productivity and a motor having a long service life and a high reliability using the oil retaining bearing unit can be provided.

    摘要翻译： 用于支撑旋转轴1的止油轴承构件2a和2b以间隔布置在轴承壳体7中。 轴承壳体7具有底部，一端打开，另一端封闭。 用于供给润滑油的多孔隔离物3紧密地插入在保油轴承2a和2b之间。 在轴承壳体7的上部配置有排油装置8，在下部配置止推轴承5。 轴承壳体7的开口端设置在上部，轴承壳体7的另一端设置在轴承壳体7的下部，并且将润滑油4a封闭在壳体中以将部件 多孔隔离物3的一部分。 多孔隔离物3的孔径大于油保持轴承2a和2b的孔径。 通过利用毛细管作用于多孔隔离物3，将润滑油4a供给至保油轴承2a。 因此，可以提供具有优异的性能和优异的质量生产率的油保持轴承单元和具有使用寿命长并且使用油保持轴承单元的高可靠性的电动机。

    Magnetic disk unit and manufacturing method of carriage structure thereof
    20.
    发明授权
    Magnetic disk unit and manufacturing method of carriage structure thereof 失效
    磁盘单元及其托架结构的制造方法

    公开(公告)号：US5301078A

    公开(公告)日：1994-04-05

    申请号：US713994

    申请日：1991-06-12

    申请人： Toshiaki Makino ,  Marutomo Goto ,  Hideyuki Kimura ,  Takashi Yamaguchi ,  Hiromu Hirai ,  Takashi Kono ,  Ryoji Okada ,  Toshihiro Yamada ,  Yasuhiro Yoshimura ,  Hideaki Amano ,  Akio Takatsuka ,  Toshio Matsushita ,  Satoru Yamaura ,  Yuichi Koizumi

    发明人： Toshiaki Makino ,  Marutomo Goto ,  Hideyuki Kimura ,  Takashi Yamaguchi ,  Hiromu Hirai ,  Takashi Kono ,  Ryoji Okada ,  Toshihiro Yamada ,  Yasuhiro Yoshimura ,  Hideaki Amano ,  Akio Takatsuka ,  Toshio Matsushita ,  Satoru Yamaura ,  Yuichi Koizumi

    IPC分类号： G11B5/48 ,  G11B21/16

    CPC分类号： G11B5/4813

    摘要： A magnetic disk unit comprising a one-piece carriage structure having a small thermal off-tracking amount, with the carriage structure including a rotary shaft; guide arms integrally supported on a guide-arm retainer at their proximal ends and extending independently and parallely; bearing retainers formed on both ends of the guide-arm retainer; and bearings fixed on the bearing retainers rotatably connecting the guide-arm retainer to the rotary shaft. A center line in a direction of thickness of the outermost guide arm is located outside of that of the bearing in a direction of height thereof, and a concave portion is continuously formed on the bearing retainer. Thermal coefficients of expansion of the guide arms and the guide-arm retainer are substantially equal, with the carriage structure being fashioned of an alloy mainly containing Al and Si, eutectic crystal Si particles in the guide arm and/or the guide-arm retainer. The average value of the longest eutectic crystal Si particles therein is 1.6 .mu.m or less or the number of the eutectic crystal Si particles if 5.0 or more per 100 .mu.m.sup.2. In the carriage of manufacturing the carriage of the carriage structure is heated for five to fifteen hours at a temperature of 300.degree. to 500.degree. C. after die casting.

    摘要翻译： 一种磁盘单元，包括具有小的热跟踪量小的单件托架结构，其中托架结构包括旋转轴; 引导臂在其近端处一体地支撑在引导臂保持器上并且独立且平行地延伸; 形成在引导臂保持器的两端的轴承保持器; 和固定在轴承保持器上的轴承，其将导向臂保持件可旋转地连接到旋转轴。 最外侧引导臂的厚度方向的中心线位于轴承的高度方向的外侧，在轴承保持架上连续地形成有凹部。 引导臂和引导臂保持器的热膨胀系数基本相等，托架结构由主要包含Al和Si的合金，共晶晶体Si颗粒在引导臂和/或引导臂保持器中形成。 其中最长的共晶晶体Si颗粒的平均值为1.6（my）m或更小，如果每100（m 2）m 2为5.0或更多，则共晶晶体Si颗粒的数量。 在制造的托架中，在铸造后，在300度至500度的温度下加热托架结构的托架5至15小时。