公开(公告)号：US07777548B2

公开(公告)日：2010-08-17

申请号：US12215774

申请日：2008-06-30

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03L5/00

CPC classification number: H03K3/35613 ,  H03K3/012

Abstract: A level shifter includes a level shifting unit for level-shifting an input signal at a first voltage level into a signal at a second voltage level, and an output controller for controlling the level shifting unit to maintain output at a predetermined logic level in response to a deep power down mode signal generated from power which is not turned off in a deep power down mode.

Abstract translation: 电平移位器包括电平移位单元，用于将处于第一电压电平的输入信号电平转换为第二电压电平的信号;以及输出控制器，用于控制电平移位单元，以响应于电平移位单元将输出保持在预定逻辑电平 在深度掉电模式下从未关闭的电源产生的深度掉电模式信号。

公开(公告)号：US07154806B2

公开(公告)日：2006-12-26

申请号：US11122692

申请日：2005-05-05

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C8/00 ,  G11C7/02

CPC classification number: G11C7/06

Abstract: Disclosed herein is a differential amplifier control circuit in which a signal indicating that all banks are not activated is provided to a differential amplifier, so that the differential amplifier does not operate, thereby reducing unnecessary current consumption in an ICC2N situation. An all bank idle notification unit generates an all bank idle signal notifying that a plurality of banks are not activated using a plurality of bank active signals for activating the plurality of the banks. A differential amplifier controller generates a differential amplifier control signal for disabling a differential amplifier using an all bank idle signal and an internal clock signal. The differential amplifier does not operate in response to the differential amplifier control signal if the plurality of the banks is all inactivated.

Abstract translation: 这里公开了一种差分放大器控制电路，其中指示所有存储体未被激活的信号被提供给差分放大器，使得差分放大器不工作，从而减少ICC2N情况下的不必要的电流消耗。 所有存储体空闲通知单元产生通过使用多个用于激活多个存储体的存储体活动信号来激活多个存储体的全部组空闲信号。 差分放大器控制器产生用于使用全部空闲信号和内部时钟信号来禁用差分放大器的差分放大器控制信号。 如果多个存储体全部被去激活，则差分放大器不响应于差分放大器控制信号而不工作。

公开(公告)号：US08854903B2

公开(公告)日：2014-10-07

申请号：US13356977

申请日：2012-01-24

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1072 ,  G11C7/1087

Abstract: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.

Abstract translation: 数据对准电路包括：选择传输单元，被配置为响应于控制信号，选择性地发送作为第一控制脉冲的第一脉冲或接地电压并选择性地传输第二脉冲或接地电压作为第二控制脉冲; 以及数据锁存单元，被配置为响应于所述第一和第二脉冲以及所述第一和第二控制脉冲来锁存数据，并且产生第一到第四数据。

公开(公告)号：US08139423B2

公开(公告)日：2012-03-20

申请号：US12939614

申请日：2010-11-04

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/06

CPC classification number: H03M9/00 ,  G11C7/1087 ,  G11C7/1096 ,  H03K3/356121 ,  H03K5/1534

Abstract: A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in response to a transition timing of a data strobe signal. The duration signal generation unit is configured to generate a duration signal which is enabled during a predetermined duration in response to a write command. The data input clock pulse generation unit is configured to generate a data input clock pulse for transferring data to a global line in response to the alignment signal within an enable duration of the duration signal.

Abstract translation: 写驱动装置包括缓冲单元，持续时间信号生成单元和数据输入时钟脉冲生成单元。 缓冲单元被配置为响应于数据选通信号的转变定时产生对准信号。 持续时间信号生成单元被配置为产生响应于写入命令在预定持续时间期间使能的持续时间信号。 数据输入时钟脉冲生成单元被配置为响应于持续时间信号的使能持续时间内的对准信号而生成用于将数据传送到全局线的数据输入时钟脉冲。

公开(公告)号：US07741892B2

公开(公告)日：2010-06-22

申请号：US12215456

申请日：2008-06-27

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C1/18

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.

Abstract translation: 公开了一种数据输出控制器，其包括使能信号控制器，其响应于DQ关闭信号和写入信号产生具有预定脉冲宽度的控制信号，并响应于读取信号和控制信号产生时钟使能信号 在读取信号被激活时与控制信号同步;以及时钟发生器，其在使能信号的激活周期期间接收使能信号和内部时钟信号，并与内部时钟信号同步地产生数据时钟信号。

公开(公告)号：US20090154267A1

公开(公告)日：2009-06-18

申请号：US12156859

申请日：2008-06-05

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C11/00 ,  H03L7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254 ,  H03K5/131

Abstract: A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.

Abstract translation: 描述了具有时钟信号发生电路的半导体存储器件，该时钟信号产生电路能够通过基于熔丝切断来控制上升和下降时钟信号的输出定时来控制符合PVT波动的数据输出。 时钟信号发生电路包括：熔丝单元，用于基于熔丝的熔丝切割产生第一和第二熔丝信号;控制信号产生单元，用于响应于熔丝信号产生第一和第二熔丝信号;时钟信号延迟单元， 延迟时钟信号，通过由控制信号指定的延迟部分延迟外部时钟信号;以及时钟产生单元，用于与延迟时钟信号的上升沿同步地产生第一内部时钟信号，并产生第二内部时钟信号 与延迟的时钟信号的下降沿同步。

公开(公告)号：US20090153262A1

公开(公告)日：2009-06-18

申请号：US12217203

申请日：2008-07-01

Applicant: Tae Jin Kang ,  Seung Hyun Ryu

Inventor： Tae Jin Kang ,  Seung Hyun Ryu

IPC: H01P5/12

CPC classification number: H04B1/48

Abstract: A repeater of a global input/output line includes a data transmitter including first and second drivers for outputting data signals of the global input/output line through different transmission routes in response to a transmission direction control signal, and a third driver for driving the global input/output line in response to an output signal of the data transmitter.

Abstract translation: 全局输入/输出线的中继器包括数据发射器，其包括用于响应于传输方向控制信号通过不同传输路由输出全局输入/输出线的数据信号的第一和第二驱动器，以及用于驱动全局 响应于数据发射器的输出信号的输入/输出线。

公开(公告)号：US20090115478A1

公开(公告)日：2009-05-07

申请号：US12215456

申请日：2008-06-27

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03L7/00

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.

Abstract translation: 公开了一种数据输出控制器，其包括使能信号控制器，其响应于DQ关闭信号和写入信号产生具有预定脉冲宽度的控制信号，并响应于读取信号和控制信号产生时钟使能信号 在读取信号被激活时与控制信号同步;以及时钟发生器，其在使能信号的激活周期期间接收使能信号和内部时钟信号，并与内部时钟信号同步地产生数据时钟信号。

公开(公告)号：US09058859B2

公开(公告)日：2015-06-16

申请号：US13617637

申请日：2012-09-14

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C7/222

Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.

Abstract translation: 数据输出电路包括：控制信号生成块，被配置为生成在第一读取操作中产生的第一传送控制信号和在第二读取操作中产生的第二传送控制信号，其中第一传送控制信号和第二传送控制信号 传入控制信号在进入测试模式时产生; 以及使能信号生成单元，被配置为响应于第一和第二传送控制信号而产生用于产生第一和第二内部时钟的第一和第二使能信号。

公开(公告)号：US08867302B2

公开(公告)日：2014-10-21

申请号：US13096669

申请日：2011-04-28

Applicant: Kyoung Hwan Kwon ,  Tae Jin Kang ,  Sang Kwon Lee

Inventor： Kyoung Hwan Kwon ,  Tae Jin Kang ,  Sang Kwon Lee

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Abstract translation: 数据输入电路包括时钟采样单元，最终时钟产生单元和写入锁存信号产生单元。 采样单元被配置为产生包括在写入等待时间之后产生的脉冲的移位信号，并且在从产生移位信号的脉冲的时间开始的脉冲串周期期间，通过对内部时钟进行采样来产生采样时钟。 最终时钟生成单元被配置为通过与采样时钟同步地锁存移位信号来产生电平信号，并且响应于突发信号从电平信号产生最终时钟。 写锁存信号生成单元被配置为通过锁存最终时钟来产生使能信号，并且响应于使能信号产生用于锁存和输出对准数据的写锁存信号。