公开(公告)号：US11855193B2

公开(公告)日：2023-12-26

申请号：US17648166

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Chieh-Wei Chen ,  Tzu-Ang Chiang

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/845 ,  H01L29/7854

Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

公开(公告)号：US20220328683A1

公开(公告)日：2022-10-13

申请号：US17852755

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US12278288B2

公开(公告)日：2025-04-15

申请号：US18673615

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US12272598B2

公开(公告)日：2025-04-08

申请号：US17818587

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： U-Ting Chiu ,  Po-Nan Yeh ,  Yu-Shih Wang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535

Abstract: A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

公开(公告)号：US12051619B2

公开(公告)日：2024-07-30

申请号：US17871042

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/76804 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5329

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20240136183A1

公开(公告)日：2024-04-25

申请号：US18402563

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0274 ,  H01L21/308 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20220359741A1

公开(公告)日：2022-11-10

申请号：US17814865

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd,

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

公开(公告)号：US12021145B2

公开(公告)日：2024-06-25

申请号：US18357794

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US11996324B2

公开(公告)日：2024-05-28

申请号：US17193201

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： U-Ting Chiu ,  Po-Nan Yeh ,  Yu-Shih Wang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/535

Abstract: A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

公开(公告)号：US11978801B2

公开(公告)日：2024-05-07

申请号：US17814865

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.