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    Systems and methods for fabricating FinFETs with different threshold voltages
    12.
    发明授权
    Systems and methods for fabricating FinFETs with different threshold voltages 有权

    公开(公告)号：US11362087B2

    公开(公告)日：2022-06-14

    申请号：US16049248

    申请日：2018-07-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chi-Wen Liu ,  Chao-Hsiung Wang

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

    Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

    DEEPLY BURIED COLOR FILTER ARRAY (CFA) BY STACKED GRID STRUCTURE
    14.
    发明申请
    DEEPLY BURIED COLOR FILTER ARRAY (CFA) BY STACKED GRID STRUCTURE 审中-公开
    通过堆叠网格结构沉浸彩色滤色片阵列（CFA）

    公开(公告)号：US20160307942A1

    公开(公告)日：2016-10-20

    申请号：US14688094

    申请日：2015-04-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yun-Wei Cheng ,  Horng-Huei Tseng ,  Chao-Hsiung Wang ,  Chun-Hao Chou ,  Tsung-Han Tsai ,  Kuo-Cheng Lee ,  Yung-Lung Hsu

    IPC: H01L27/146

    CPC classification number: H01L27/1464 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14685

    Abstract: The present disclosure relates to a BSI image sensor having a color filter disposed between sidewalls of a metallic grid, and a method of formation. In some embodiments, the BSI image sensor has a pixel sensor located within a semiconductor substrate, and a layer of dielectric material overlying the pixel sensor. A metallic grid is separated from the semiconductor substrate by the layer of dielectric material, and a stacked grid is arranged over the metallic grid. The stacked grid abuts an opening that vertically extends from an upper surface of the stacked grid to a position that is laterally arranged between sidewalls of the metallic grid. A color filter can be arranged within the opening. By having the color filter vertically extend between sidewalls of the metallic grid, a distance between the color filter and the pixel sensor can be made small, thereby improving performance of the BSI image sensor.

    Abstract translation: 本公开涉及一种具有布置在金属网格的侧壁之间的滤色器的BSI图像传感器和形成方法。 在一些实施例中，BSI图像传感器具有位于半导体衬底内的像素传感器和覆盖在像素传感器上的介电材料层。 通过介电材料层将金属栅格与半导体衬底分开，并且在金属栅格上方布置有堆叠栅格。 堆叠的网格邻接从堆叠网格的上表面垂直延伸到横向布置在金属网格的侧壁之间的位置的开口。 可以在开口内布置滤色器。 通过使滤色器在金属网格的侧壁之间垂直延伸，可以使滤色器和像素传感器之间的距离较小，从而提高BSI图像传感器的性能。

    FinFet device with channel epitaxial region
    19.
    发明授权
    FinFet device with channel epitaxial region 有权
    FinFet器件具有沟道外延区域

    公开(公告)号：US09496397B2

    公开(公告)日：2016-11-15

    申请号：US13970790

    申请日：2013-08-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Chao-Hsiung Wang ,  Chi-Wen Liu

    IPC: H01L29/78 ,  H01L21/76 ,  H01L29/66 ,  H01L21/762

    CPC classification number: H01L29/785 ,  H01L21/76 ,  H01L21/76229 ,  H01L29/66795

    Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.

    Abstract translation: 本公开涉及具有外延增强结构的Fin场效应晶体管（FinFET）器件及其相关制造方法。 在一些实施例中，FinFET器件具有半导体衬底，其具有覆盖半导体衬底的多个隔离区域。 在多个隔离区域之间的位置处，多个三维翅片从半导体衬底的顶表面突出。 相应的三维翅片具有向三维翅片引入应变的外延增强结构。 外延增强结构被布置在三维鳍片内的半导体材料上方，位于相邻隔离区域的底部之上超过10纳米的位置。 在这样的位置形成外延增强结构提供足够的结构支撑以避免隔离区域崩溃。

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