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    CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY
    11.
    发明申请
    CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY 有权

    公开(公告)号：US20210193566A1

    公开(公告)日：2021-06-24

    申请号：US16885378

    申请日：2020-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

    IPC: H01L23/522 ,  H01L23/538 ,  H01L21/768

    Abstract: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.

    METAL CAPPING LAYER AND METHODS THEREOF
    13.
    发明申请
    METAL CAPPING LAYER AND METHODS THEREOF 审中-公开

    公开(公告)号：US20200006116A1

    公开(公告)日：2020-01-02

    申请号：US16270057

    申请日：2019-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan LEE ,  Cheng-Chin Lee ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

    Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

    SELECTIVE DEPOSITION FOR INTEGRATED CIRCUIT INTERCONNECT STRUCTURES
    15.
    发明申请
    SELECTIVE DEPOSITION FOR INTEGRATED CIRCUIT INTERCONNECT STRUCTURES 有权

    公开(公告)号：US20220277996A1

    公开(公告)日：2022-09-01

    申请号：US17745614

    申请日：2022-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

    Capping layer overlying dielectric structure to increase reliability
    16.
    发明授权
    Capping layer overlying dielectric structure to increase reliability 有权

    公开(公告)号：US11355430B2

    公开(公告)日：2022-06-07

    申请号：US16885378

    申请日：2020-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

    IPC: H01L23/522 ,  H01L23/538 ,  H01L21/768

    Abstract: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.

    Selective deposition for integrated circuit interconnect structures
    17.
    发明授权
    Selective deposition for integrated circuit interconnect structures 有权

    公开(公告)号：US11335596B2

    公开(公告)日：2022-05-17

    申请号：US16577079

    申请日：2019-09-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

    Dielectric capping structure overlying a conductive structure to increase stability
    18.
    发明授权
    Dielectric capping structure overlying a conductive structure to increase stability 有权

    公开(公告)号：US11322395B2

    公开(公告)日：2022-05-03

    申请号：US16876432

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.

    Metal capping layer and methods thereof
    20.
    发明授权
    Metal capping layer and methods thereof 有权

    公开(公告)号：US11075113B2

    公开(公告)日：2021-07-27

    申请号：US16270057

    申请日：2019-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321

    Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

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