公开(公告)号：US11658092B2

公开(公告)日：2023-05-23

申请号：US17097441

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367

CPC分类号： H01L23/373 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/53295

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US11450566B2

公开(公告)日：2022-09-20

申请号：US17121661

申请日：2020-12-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Shao-Kuan Lee ,  Hai-Ching Chen

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

摘要： A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

公开(公告)号：US11302798B2

公开(公告)日：2022-04-12

申请号：US16888138

申请日：2020-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

摘要： A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.

公开(公告)号：US20140225261A1

公开(公告)日：2014-08-14

申请号：US14258175

申请日：2014-04-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

IPC分类号： H01L23/485 ,  H01L23/482

CPC分类号： H01L23/4827 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.

摘要翻译： 本公开的一些实施例涉及用于连接半导体衬底的器件的互连结构。 所述互连结构包括在所述衬底上的电介质层和穿过所述电介质层的连续导电体。 连续导电体由下体区域和上体区域构成。 下体区域具有限定在连续导电体的相对的下侧壁之间的第一宽度，并且上体区域具有限定在连续导电体的相对的上侧壁之间的第二宽度。 第二宽度小于第一宽度。 阻挡层将连续导电体与电介质层分开。

公开(公告)号：US20240347625A1

公开(公告)日：2024-10-17

申请号：US18752172

申请日：2024-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823468 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

公开(公告)号：US12027606B2

公开(公告)日：2024-07-02

申请号：US17717684

申请日：2022-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823468 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

公开(公告)号：US20220238693A1

公开(公告)日：2022-07-28

申请号：US17717684

申请日：2022-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

摘要： A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

公开(公告)号：US20220157711A1

公开(公告)日：2022-05-19

申请号：US17097505

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Cheng-Chin Lee ,  Kuang-Wei Yang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/768

摘要： The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

公开(公告)号：US20220157690A1

公开(公告)日：2022-05-19

申请号：US17097441

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L23/48 ,  H01L21/768

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US20210193505A1

公开(公告)日：2021-06-24

申请号：US16876432

申请日：2020-05-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC分类号： H01L21/768 ,  H01L23/532

摘要： Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.