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    FIELD PLATE AND ISOLATION STRUCTURE FOR HIGH VOLTAGE DEVICE
    11.
    发明申请
    FIELD PLATE AND ISOLATION STRUCTURE FOR HIGH VOLTAGE DEVICE 有权

    公开(公告)号：US20210296451A1

    公开(公告)日：2021-09-23

    申请号：US16821247

    申请日：2020-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kaochao Chen ,  Chia-Cheng Ho ,  Ming Chyi Liu

    IPC: H01L29/40 ,  H01L21/768 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3105

    Abstract: An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.

    Field plate structure to enhance transistor breakdown voltage
    12.
    发明授权
    Field plate structure to enhance transistor breakdown voltage 有权

    公开(公告)号：US11121225B2

    公开(公告)日：2021-09-14

    申请号：US16671336

    申请日：2019-11-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Cheng Ho ,  Ming-Ta Lei ,  Yu-Chang Jong

    IPC: H01L29/40 ,  H01L29/66 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L29/78

    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate electrode overlies a substrate between a source region and a drain region. A drift region is arranged laterally between the gate electrode and the drain region. A plurality of inter-level dielectric (ILD) layers overlie the substrate. The plurality of ILD layers includes a first ILD layer underlying a second ILD layer. A plurality of conductive interconnect layers is disposed within the plurality of ILD layers. The field plate extends from a top surface of the first ILD layer to a point that is vertically separated from the drift region by the first ILD layer. The field plate is laterally offset the gate electrode by a non-zero distance in a direction toward the drain region. The field plate includes a same material as at least one of the plurality of conductive interconnect layers.

    Ferroelectric Semiconductor Device and Method
    17.
    发明申请
    Ferroelectric Semiconductor Device and Method 有权

    公开(公告)号：US20220367718A1

    公开(公告)日：2022-11-17

    申请号：US17874466

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

    IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

    Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

    Strained transistor with conductive plate
    20.
    发明授权
    Strained transistor with conductive plate 有权

    公开(公告)号：US12166108B2

    公开(公告)日：2024-12-10

    申请号：US17747104

    申请日：2022-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chan-Yu Hung ,  Chia-Cheng Ho ,  Fei-Yun Chen ,  Yu-Chang Jong ,  Puo-Yu Chiang ,  Tun-Yi Ho

    IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

    Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

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